branch.isa (9552:460cf901acba) | branch.isa (10184:bbfa3152bdea) |
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1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 34 unchanged lines hidden (view full) --- 43 public: 44 // Constructor 45 %(class_name)s(ExtMachInst machInst, int32_t _imm); 46 %(BasicExecDeclare)s 47}; 48}}; 49 50def template BranchImmConstructor {{ | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2010 ARM Limited 4// All rights reserved 5// 6// The license below extends only to copyright in the software and shall 7// not be construed as granting a license to any other intellectual 8// property including but not limited to intellectual property relating --- 34 unchanged lines hidden (view full) --- 43 public: 44 // Constructor 45 %(class_name)s(ExtMachInst machInst, int32_t _imm); 46 %(BasicExecDeclare)s 47}; 48}}; 49 50def template BranchImmConstructor {{ |
51 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, | 51 %(class_name)s::%(class_name)s(ExtMachInst machInst, |
52 int32_t _imm) 53 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 54 { 55 %(constructor)s; 56 if (!(condCode == COND_AL || condCode == COND_UC)) { 57 for (int x = 0; x < _numDestRegs; x++) { 58 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 59 } --- 16 unchanged lines hidden (view full) --- 76 ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 77 78 /// Explicitly import the otherwise hidden branchTarget 79 using StaticInst::branchTarget; 80}; 81}}; 82 83def template BranchImmCondConstructor {{ | 52 int32_t _imm) 53 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm) 54 { 55 %(constructor)s; 56 if (!(condCode == COND_AL || condCode == COND_UC)) { 57 for (int x = 0; x < _numDestRegs; x++) { 58 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 59 } --- 16 unchanged lines hidden (view full) --- 76 ArmISA::PCState branchTarget(const ArmISA::PCState &branchPC) const; 77 78 /// Explicitly import the otherwise hidden branchTarget 79 using StaticInst::branchTarget; 80}; 81}}; 82 83def template BranchImmCondConstructor {{ |
84 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, | 84 %(class_name)s::%(class_name)s(ExtMachInst machInst, |
85 int32_t _imm, 86 ConditionCode _condCode) 87 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 88 _imm, _condCode) 89 { 90 %(constructor)s; 91 if (!(condCode == COND_AL || condCode == COND_UC)) { 92 for (int x = 0; x < _numDestRegs; x++) { --- 12 unchanged lines hidden (view full) --- 105 public: 106 // Constructor 107 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); 108 %(BasicExecDeclare)s 109}; 110}}; 111 112def template BranchRegConstructor {{ | 85 int32_t _imm, 86 ConditionCode _condCode) 87 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 88 _imm, _condCode) 89 { 90 %(constructor)s; 91 if (!(condCode == COND_AL || condCode == COND_UC)) { 92 for (int x = 0; x < _numDestRegs; x++) { --- 12 unchanged lines hidden (view full) --- 105 public: 106 // Constructor 107 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1); 108 %(BasicExecDeclare)s 109}; 110}}; 111 112def template BranchRegConstructor {{ |
113 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, | 113 %(class_name)s::%(class_name)s(ExtMachInst machInst, |
114 IntRegIndex _op1) 115 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) 116 { 117 %(constructor)s; 118 if (!(condCode == COND_AL || condCode == COND_UC)) { 119 for (int x = 0; x < _numDestRegs; x++) { 120 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 121 } --- 13 unchanged lines hidden (view full) --- 135 // Constructor 136 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, 137 ConditionCode _condCode); 138 %(BasicExecDeclare)s 139}; 140}}; 141 142def template BranchRegCondConstructor {{ | 114 IntRegIndex _op1) 115 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1) 116 { 117 %(constructor)s; 118 if (!(condCode == COND_AL || condCode == COND_UC)) { 119 for (int x = 0; x < _numDestRegs; x++) { 120 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; 121 } --- 13 unchanged lines hidden (view full) --- 135 // Constructor 136 %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, 137 ConditionCode _condCode); 138 %(BasicExecDeclare)s 139}; 140}}; 141 142def template BranchRegCondConstructor {{ |
143 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, | 143 %(class_name)s::%(class_name)s(ExtMachInst machInst, |
144 IntRegIndex _op1, 145 ConditionCode _condCode) 146 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 147 _op1, _condCode) 148 { 149 %(constructor)s; 150 if (!(condCode == COND_AL || condCode == COND_UC)) { 151 for (int x = 0; x < _numDestRegs; x++) { --- 30 unchanged lines hidden (view full) --- 182 183 %(InitiateAccDeclare)s 184 185 %(CompleteAccDeclare)s 186}; 187}}; 188 189def template BranchRegRegConstructor {{ | 144 IntRegIndex _op1, 145 ConditionCode _condCode) 146 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, 147 _op1, _condCode) 148 { 149 %(constructor)s; 150 if (!(condCode == COND_AL || condCode == COND_UC)) { 151 for (int x = 0; x < _numDestRegs; x++) { --- 30 unchanged lines hidden (view full) --- 182 183 %(InitiateAccDeclare)s 184 185 %(CompleteAccDeclare)s 186}; 187}}; 188 189def template BranchRegRegConstructor {{ |
190 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, | 190 %(class_name)s::%(class_name)s(ExtMachInst machInst, |
191 IntRegIndex _op1, 192 IntRegIndex _op2) 193 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) 194 { 195 %(constructor)s; 196 if (!(condCode == COND_AL || condCode == COND_UC)) { 197 for (int x = 0; x < _numDestRegs; x++) { 198 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; --- 14 unchanged lines hidden (view full) --- 213 int32_t imm, IntRegIndex _op1); 214 %(BasicExecDeclare)s 215}; 216}}; 217 218// Only used by CBNZ, CBZ which is conditional based on 219// a register value even though the instruction is always unconditional. 220def template BranchImmRegConstructor {{ | 191 IntRegIndex _op1, 192 IntRegIndex _op2) 193 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2) 194 { 195 %(constructor)s; 196 if (!(condCode == COND_AL || condCode == COND_UC)) { 197 for (int x = 0; x < _numDestRegs; x++) { 198 _srcRegIdx[_numSrcRegs++] = _destRegIdx[x]; --- 14 unchanged lines hidden (view full) --- 213 int32_t imm, IntRegIndex _op1); 214 %(BasicExecDeclare)s 215}; 216}}; 217 218// Only used by CBNZ, CBZ which is conditional based on 219// a register value even though the instruction is always unconditional. 220def template BranchImmRegConstructor {{ |
221 inline %(class_name)s::%(class_name)s(ExtMachInst machInst, | 221 %(class_name)s::%(class_name)s(ExtMachInst machInst, |
222 int32_t _imm, 223 IntRegIndex _op1) 224 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) 225 { 226 %(constructor)s; 227 flags[IsCondControl] = true; 228 } 229}}; --- 17 unchanged lines hidden --- | 222 int32_t _imm, 223 IntRegIndex _op1) 224 : %(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1) 225 { 226 %(constructor)s; 227 flags[IsCondControl] = true; 228 } 229}}; --- 17 unchanged lines hidden --- |