| operands.isa (8449:4be49ad47c74) | operands.isa (9251:5d0fcec59036) |
|---|---|
| 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 104 unchanged lines hidden (view full) --- 113 def intRegAIWPC(idx): 114 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal, 115 maybePCRead, maybeAIWPCWrite) 116 117 def intRegCC(idx): 118 return ('IntReg', 'uw', idx, None, srtNormal) 119 120 def cntrlReg(idx, id = srtNormal, type = 'uw'): | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 104 unchanged lines hidden (view full) --- 113 def intRegAIWPC(idx): 114 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal, 115 maybePCRead, maybeAIWPCWrite) 116 117 def intRegCC(idx): 118 return ('IntReg', 'uw', idx, None, srtNormal) 119 120 def cntrlReg(idx, id = srtNormal, type = 'uw'): |
| 121 return ('ControlReg', type, idx, (None, None, 'IsControl'), id) | 121 return ('ControlReg', type, idx, None, id) |
| 122 123 def cntrlRegNC(idx, id = srtNormal, type = 'uw'): 124 return ('ControlReg', type, idx, None, id) 125 126 def pcStateReg(idx, id): 127 return ('PCState', 'uw', idx, (None, None, 'IsControl'), id) 128}}; 129 --- 152 unchanged lines hidden --- | 122 123 def cntrlRegNC(idx, id = srtNormal, type = 'uw'): 124 return ('ControlReg', type, idx, None, id) 125 126 def pcStateReg(idx, id): 127 return ('PCState', 'uw', idx, (None, None, 'IsControl'), id) 128}}; 129 --- 152 unchanged lines hidden --- |