| operands.isa (8302:9f23d01421de) | operands.isa (8303:5a95f1d2494e) |
|---|---|
| 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 142 unchanged lines hidden (view full) --- 151 'R7': intRegNPC('7'), 152 # First four arguments are passed in registers 153 'R0': intRegNPC('0'), 154 'R1': intRegNPC('1'), 155 'R2': intRegNPC('2'), 156 'R3': intRegNPC('3'), 157 158 #Pseudo integer condition code registers | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 142 unchanged lines hidden (view full) --- 151 'R7': intRegNPC('7'), 152 # First four arguments are passed in registers 153 'R0': intRegNPC('0'), 154 'R1': intRegNPC('1'), 155 'R2': intRegNPC('2'), 156 'R3': intRegNPC('3'), 157 158 #Pseudo integer condition code registers |
| 159 'CondCodesF': intRegCC('INTREG_CONDCODES_F'), | 159 'CondCodesNZ': intRegCC('INTREG_CONDCODES_NZ'), 160 'CondCodesC': intRegCC('INTREG_CONDCODES_C'), 161 'CondCodesV': intRegCC('INTREG_CONDCODES_V'), |
| 160 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'), | 162 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'), |
| 161 'OptCondCodesF': intRegCC( 162 '''(condCode == COND_AL || condCode == COND_UC) ? 163 INTREG_ZERO : INTREG_CONDCODES_F'''), | 163 'OptCondCodesNZ': intRegCC( 164 '''(condCode == COND_AL || condCode == COND_UC || 165 condCode == COND_CC || condCode == COND_CS || 166 condCode == COND_VS || condCode == COND_VC) ? 167 INTREG_ZERO : INTREG_CONDCODES_NZ'''), 168 'OptCondCodesC': intRegCC( 169 '''(condCode == COND_HI || condCode == COND_LS || 170 condCode == COND_CS || condCode == COND_CC) ? 171 INTREG_CONDCODES_C : INTREG_ZERO'''), 172 'OptCondCodesV': intRegCC( 173 '''(condCode == COND_VS || condCode == COND_VC || 174 condCode == COND_GE || condCode == COND_LT || 175 condCode == COND_GT || condCode == COND_LE) ? 176 INTREG_CONDCODES_V : INTREG_ZERO'''), |
| 164 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'), 165 166 #Abstracted floating point reg operands 167 'FpDest': floatReg('(dest + 0)'), 168 'FpDestP0': floatReg('(dest + 0)'), 169 'FpDestP1': floatReg('(dest + 1)'), 170 'FpDestP2': floatReg('(dest + 2)'), 171 'FpDestP3': floatReg('(dest + 3)'), --- 92 unchanged lines hidden --- | 177 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'), 178 179 #Abstracted floating point reg operands 180 'FpDest': floatReg('(dest + 0)'), 181 'FpDestP0': floatReg('(dest + 0)'), 182 'FpDestP1': floatReg('(dest + 1)'), 183 'FpDestP2': floatReg('(dest + 2)'), 184 'FpDestP3': floatReg('(dest + 3)'), --- 92 unchanged lines hidden --- |