| operands.isa (8209:9e3f7f00fa90) | operands.isa (8301:858384f3af1c) |
|---|---|
| 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 142 unchanged lines hidden (view full) --- 151 'R7': intRegNPC('7'), 152 # First four arguments are passed in registers 153 'R0': intRegNPC('0'), 154 'R1': intRegNPC('1'), 155 'R2': intRegNPC('2'), 156 'R3': intRegNPC('3'), 157 158 #Pseudo integer condition code registers | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 142 unchanged lines hidden (view full) --- 151 'R7': intRegNPC('7'), 152 # First four arguments are passed in registers 153 'R0': intRegNPC('0'), 154 'R1': intRegNPC('1'), 155 'R2': intRegNPC('2'), 156 'R3': intRegNPC('3'), 157 158 #Pseudo integer condition code registers |
| 159 'CondCodes': intRegCC('INTREG_CONDCODES'), 160 'OptCondCodes': intRegCC( | 159 'CondCodesF': intRegCC('INTREG_CONDCODES_F'), 160 'CondCodesQ': intRegCC('INTREG_CONDCODES_Q'), 161 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'), 162 'OptCondCodesF': intRegCC( |
| 161 '''(condCode == COND_AL || condCode == COND_UC) ? | 163 '''(condCode == COND_AL || condCode == COND_UC) ? |
| 162 INTREG_ZERO : INTREG_CONDCODES'''), | 164 INTREG_ZERO : INTREG_CONDCODES_F'''), |
| 163 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'), 164 165 #Abstracted floating point reg operands 166 'FpDest': floatReg('(dest + 0)'), 167 'FpDestP0': floatReg('(dest + 0)'), 168 'FpDestP1': floatReg('(dest + 1)'), 169 'FpDestP2': floatReg('(dest + 2)'), 170 'FpDestP3': floatReg('(dest + 3)'), --- 91 unchanged lines hidden --- | 165 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'), 166 167 #Abstracted floating point reg operands 168 'FpDest': floatReg('(dest + 0)'), 169 'FpDestP0': floatReg('(dest + 0)'), 170 'FpDestP1': floatReg('(dest + 1)'), 171 'FpDestP2': floatReg('(dest + 2)'), 172 'FpDestP3': floatReg('(dest + 3)'), --- 91 unchanged lines hidden --- |