| operands.isa (8204:6c051a8df26a) | operands.isa (8205:7ecbffb674aa) |
|---|---|
| 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 203 unchanged lines hidden (view full) --- 212 'FpOp2P3': floatReg('(op2 + 3)'), 213 214 #Abstracted control reg operands 215 'MiscDest': cntrlReg('dest'), 216 'MiscOp1': cntrlReg('op1'), 217 218 #Fixed index control regs 219 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr), | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 203 unchanged lines hidden (view full) --- 212 'FpOp2P3': floatReg('(op2 + 3)'), 213 214 #Abstracted control reg operands 215 'MiscDest': cntrlReg('dest'), 216 'MiscOp1': cntrlReg('op1'), 217 218 #Fixed index control regs 219 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr), |
| 220 'Itstate': cntrlRegNC('MISCREG_ITSTATE', type = 'ub'), | |
| 221 'Spsr': cntrlRegNC('MISCREG_SPSR'), 222 'Fpsr': cntrlRegNC('MISCREG_FPSR'), 223 'Fpsid': cntrlRegNC('MISCREG_FPSID'), 224 'Fpscr': cntrlRegNC('MISCREG_FPSCR'), 225 'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'), 226 'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'), 227 'Cpacr': cntrlReg('MISCREG_CPACR'), 228 'Fpexc': cntrlRegNC('MISCREG_FPEXC'), --- 13 unchanged lines hidden (view full) --- 242 #PCState fields 243 'PC': pcStateReg('instPC', srtPC), 244 'NPC': pcStateReg('instNPC', srtPC), 245 'pNPC': pcStateReg('instNPC', srtEPC), 246 'IWNPC': pcStateReg('instIWNPC', srtPC), 247 'Thumb': pcStateReg('thumb', srtPC), 248 'NextThumb': pcStateReg('nextThumb', srtMode), 249 'NextJazelle': pcStateReg('nextJazelle', srtMode), | 220 'Spsr': cntrlRegNC('MISCREG_SPSR'), 221 'Fpsr': cntrlRegNC('MISCREG_FPSR'), 222 'Fpsid': cntrlRegNC('MISCREG_FPSID'), 223 'Fpscr': cntrlRegNC('MISCREG_FPSCR'), 224 'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'), 225 'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'), 226 'Cpacr': cntrlReg('MISCREG_CPACR'), 227 'Fpexc': cntrlRegNC('MISCREG_FPEXC'), --- 13 unchanged lines hidden (view full) --- 241 #PCState fields 242 'PC': pcStateReg('instPC', srtPC), 243 'NPC': pcStateReg('instNPC', srtPC), 244 'pNPC': pcStateReg('instNPC', srtEPC), 245 'IWNPC': pcStateReg('instIWNPC', srtPC), 246 'Thumb': pcStateReg('thumb', srtPC), 247 'NextThumb': pcStateReg('nextThumb', srtMode), 248 'NextJazelle': pcStateReg('nextJazelle', srtMode), |
| 250 'ForcedItState': pcStateReg('forcedItState', srtMode), | 249 'NextItState': pcStateReg('nextItstate', srtMode), 250 'Itstate': pcStateReg('itstate', srtMode), |
| 251 252 #Register operands depending on a field in the instruction encoding. These 253 #should be avoided since they may not be portable across different 254 #encodings of the same instruction. 255 'Rd': intReg('RD'), 256 'Rm': intReg('RM'), 257 'Rs': intReg('RS'), 258 'Rn': intReg('RN'), 259 'Rt': intReg('RT') 260}}; | 251 252 #Register operands depending on a field in the instruction encoding. These 253 #should be avoided since they may not be portable across different 254 #encodings of the same instruction. 255 'Rd': intReg('RD'), 256 'Rm': intReg('RM'), 257 'Rs': intReg('RS'), 258 'Rn': intReg('RN'), 259 'Rt': intReg('RT') 260}}; |