| operands.isa (8139:2b2efc67f6df) | operands.isa (8204:6c051a8df26a) |
|---|---|
| 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 135 unchanged lines hidden (view full) --- 144 'Reg1': intReg('reg1'), 145 'Reg2': intReg('reg2'), 146 'Reg3': intReg('reg3'), 147 148 #Fixed index integer reg operands 149 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'), 150 'LR': intRegNPC('INTREG_LR'), 151 'R7': intRegNPC('7'), | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 135 unchanged lines hidden (view full) --- 144 'Reg1': intReg('reg1'), 145 'Reg2': intReg('reg2'), 146 'Reg3': intReg('reg3'), 147 148 #Fixed index integer reg operands 149 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'), 150 'LR': intRegNPC('INTREG_LR'), 151 'R7': intRegNPC('7'), |
| 152 # First four arguments are passed in registers |
|
| 152 'R0': intRegNPC('0'), | 153 'R0': intRegNPC('0'), |
| 153 'R1': intRegNPC('0'), 154 'R2': intRegNPC('1'), | 154 'R1': intRegNPC('1'), 155 'R2': intRegNPC('2'), 156 'R3': intRegNPC('3'), |
| 155 156 #Pseudo integer condition code registers 157 'CondCodes': intRegCC('INTREG_CONDCODES'), 158 'OptCondCodes': intRegCC( 159 '''(condCode == COND_AL || condCode == COND_UC) ? 160 INTREG_ZERO : INTREG_CONDCODES'''), 161 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'), 162 --- 96 unchanged lines hidden --- | 157 158 #Pseudo integer condition code registers 159 'CondCodes': intRegCC('INTREG_CONDCODES'), 160 'OptCondCodes': intRegCC( 161 '''(condCode == COND_AL || condCode == COND_UC) ? 162 INTREG_ZERO : INTREG_CONDCODES'''), 163 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'), 164 --- 96 unchanged lines hidden --- |