| operands.isa (7783:9b880b40ac10) | operands.isa (7796:9bd6b37d0189) |
|---|---|
| 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 175 unchanged lines hidden (view full) --- 184 #Register fields for microops 185 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 3, maybePCRead, maybePCWrite), 186 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 3, 187 maybePCRead, maybeIWPCWrite), 188 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 3), 189 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 3, maybePCRead, maybePCWrite), 190 'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 3, maybePCRead, maybePCWrite), 191 | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 175 unchanged lines hidden (view full) --- 184 #Register fields for microops 185 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 3, maybePCRead, maybePCWrite), 186 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 3, 187 maybePCRead, maybeIWPCWrite), 188 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 3), 189 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 3, maybePCRead, maybePCWrite), 190 'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 3, maybePCRead, maybePCWrite), 191 |
| 192 #General Purpose Floating Point Reg Operands 193 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 3), 194 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 3), 195 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3), 196 | |
| 197 #Memory Operand 198 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 3), 199 200 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 2), 201 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 3), 202 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 3), 203 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 3), 204 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 3), --- 13 unchanged lines hidden --- | 192 #Memory Operand 193 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 3), 194 195 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 2), 196 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 3), 197 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 3), 198 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 3), 199 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 3), --- 13 unchanged lines hidden --- |