Cross Reference: /gem5/src/arch/arm/isa/operands.isa

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operands.isa (7732:a2c660de7787)	operands.isa (7783:9b880b40ac10)
1// -- mode:c++ -- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 189 unchanged lines hidden (view full) --- 198 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 3), 199 200 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 2), 201 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 3), 202 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 3), 203 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 3), 204 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 3), 205 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 3),	1// -- mode:c++ -- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 189 unchanged lines hidden (view full) --- 198 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 3), 199 200 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 2), 201 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 3), 202 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 3), 203 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 3), 204 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 3), 205 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 3),
	206 'FpscrQc': ('ControlReg', 'uw', 'MISCREG_FPSCR_QC', None, 3), 207 'FpscrExc': ('ControlReg', 'uw', 'MISCREG_FPSCR_EXC', None, 3),
206 'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 3), 207 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 3), 208 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 3), 209 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 3), 210 #PCS needs to have a sorting index (the number at the end) less than all 211 #the integer registers which might update the PC. That way if the flag 212 #bits of the pc state are updated and a branch happens through R15, the 213 #updates are layered properly and the R15 update isn't lost. 214 'PCS': ('PCState', 'uw', None, (None, None, 'IsControl'), 0) 215}};	208 'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 3), 209 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 3), 210 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 3), 211 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 3), 212 #PCS needs to have a sorting index (the number at the end) less than all 213 #the integer registers which might update the PC. That way if the flag 214 #bits of the pc state are updated and a branch happens through R15, the 215 #updates are layered properly and the R15 update isn't lost. 216 'PCS': ('PCState', 'uw', None, (None, None, 'IsControl'), 0) 217}};