| operands.isa (7720:65d338a8dba4) | operands.isa (7732:a2c660de7787) |
|---|---|
| 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 156 unchanged lines hidden (view full) --- 165 maybePCRead, maybePCWrite), 166 #General Purpose Integer Reg Operands 167 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 3, maybePCRead, maybePCWrite), 168 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 3, maybePCRead, maybePCWrite), 169 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 170 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 3, maybePCRead, maybePCWrite), 171 'R7': ('IntReg', 'uw', '7', 'IsInteger', 3), 172 'R0': ('IntReg', 'uw', '0', 'IsInteger', 3), | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 156 unchanged lines hidden (view full) --- 165 maybePCRead, maybePCWrite), 166 #General Purpose Integer Reg Operands 167 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 3, maybePCRead, maybePCWrite), 168 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 3, maybePCRead, maybePCWrite), 169 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 170 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 3, maybePCRead, maybePCWrite), 171 'R7': ('IntReg', 'uw', '7', 'IsInteger', 3), 172 'R0': ('IntReg', 'uw', '0', 'IsInteger', 3), |
| 173 'R1': ('IntReg', 'uw', '0', 'IsInteger', 3), 174 'R2': ('IntReg', 'uw', '1', 'IsInteger', 3), 175 'Rt' : ('IntReg', 'uw', 'RT', 'IsInteger', 3, maybePCRead, maybePCWrite), |
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| 173 174 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 3), 175 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 3), 176 'OptCondCodes': ('IntReg', 'uw', 177 '''(condCode == COND_AL || condCode == COND_UC) ? 178 INTREG_ZERO : INTREG_CONDCODES''', None, 3), 179 'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 3), 180 --- 32 unchanged lines hidden --- | 176 177 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 3), 178 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 3), 179 'OptCondCodes': ('IntReg', 'uw', 180 '''(condCode == COND_AL || condCode == COND_UC) ? 181 INTREG_ZERO : INTREG_CONDCODES''', None, 3), 182 'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 3), 183 --- 32 unchanged lines hidden --- |