Cross Reference: /gem5/src/arch/arm/isa/operands.isa

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operands.isa (7639:8c09b7ff5b57)	operands.isa (7640:5286a8a469c5)
1// -- mode:c++ -- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 191 unchanged lines hidden (view full) --- 200 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2), 201 202 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1), 203 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 2), 204 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2), 205 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2), 206 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2), 207 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),	1// -- mode:c++ -- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 191 unchanged lines hidden (view full) --- 200 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2), 201 202 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1), 203 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 2), 204 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2), 205 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2), 206 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2), 207 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
	208 'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 2),
208 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2), 209 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2), 210 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2), 211 'PC': ('PC', 'ud', None, None, 2), 212 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 213 readNPC, writeNPC), 214 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 215 readNPC, forceNPC), 216 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 217 readNPC, writeIWNPC), 218}};	209 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2), 210 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2), 211 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2), 212 'PC': ('PC', 'ud', None, None, 2), 213 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 214 readNPC, writeNPC), 215 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 216 readNPC, forceNPC), 217 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 218 readNPC, writeIWNPC), 219}};