Cross Reference: /gem5/src/arch/arm/isa/operands.isa

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1// -- mode:c++ -- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 33 unchanged lines hidden (view full) --- 42def operand_types {{ 43 'sb' : ('signed int', 8), 44 'ub' : ('unsigned int', 8), 45 'sh' : ('signed int', 16), 46 'uh' : ('unsigned int', 16), 47 'sw' : ('signed int', 32), 48 'uw' : ('unsigned int', 32), 49 'ud' : ('unsigned int', 64),	1// -- mode:c++ -- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 33 unchanged lines hidden (view full) --- 42def operand_types {{ 43 'sb' : ('signed int', 8), 44 'ub' : ('unsigned int', 8), 45 'sh' : ('signed int', 16), 46 'uh' : ('unsigned int', 16), 47 'sw' : ('signed int', 32), 48 'uw' : ('unsigned int', 32), 49 'ud' : ('unsigned int', 64),
	50 'tud' : ('twin64 int', 64),
50 'sf' : ('float', 32), 51 'df' : ('float', 64) 52}}; 53 54let {{ 55 maybePCRead = ''' 56 ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) : 57 xc->%(func)s(this, %(op_idx)s)) --- 33 unchanged lines hidden (view full) --- 91 #Abstracted integer reg operands 92 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, 93 maybePCRead, maybePCWrite), 94 'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2), 95 'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2), 96 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2), 97 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2), 98 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2),	51 'sf' : ('float', 32), 52 'df' : ('float', 64) 53}}; 54 55let {{ 56 maybePCRead = ''' 57 ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) : 58 xc->%(func)s(this, %(op_idx)s)) --- 33 unchanged lines hidden (view full) --- 92 #Abstracted integer reg operands 93 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, 94 maybePCRead, maybePCWrite), 95 'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2), 96 'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2), 97 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2), 98 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2), 99 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2),
	100 'FpDestP4': ('FloatReg', 'sf', '(dest + 4)', 'IsFloating', 2), 101 'FpDestP5': ('FloatReg', 'sf', '(dest + 5)', 'IsFloating', 2), 102 'FpDestP6': ('FloatReg', 'sf', '(dest + 6)', 'IsFloating', 2), 103 'FpDestP7': ('FloatReg', 'sf', '(dest + 7)', 'IsFloating', 2), 104 'FpDestS0P0': ('FloatReg', 'sf', '(dest + step * 0 + 0)', 'IsFloating', 2), 105 'FpDestS0P1': ('FloatReg', 'sf', '(dest + step * 0 + 1)', 'IsFloating', 2), 106 'FpDestS1P0': ('FloatReg', 'sf', '(dest + step * 1 + 0)', 'IsFloating', 2), 107 'FpDestS1P1': ('FloatReg', 'sf', '(dest + step * 1 + 1)', 'IsFloating', 2), 108 'FpDestS2P0': ('FloatReg', 'sf', '(dest + step * 2 + 0)', 'IsFloating', 2), 109 'FpDestS2P1': ('FloatReg', 'sf', '(dest + step * 2 + 1)', 'IsFloating', 2), 110 'FpDestS3P0': ('FloatReg', 'sf', '(dest + step * 3 + 0)', 'IsFloating', 2), 111 'FpDestS3P1': ('FloatReg', 'sf', '(dest + step * 3 + 1)', 'IsFloating', 2),
99 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2, 100 maybePCRead, maybePCWrite), 101 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2, 102 maybePCRead, maybePCWrite), 103 'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2), 104 'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2), 105 'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2), 106 'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2), --- 12 unchanged lines hidden (view full) --- 119 maybePCRead, maybePCWrite), 120 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2, 121 maybePCRead, maybePCWrite), 122 'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2), 123 'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2), 124 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2), 125 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2), 126 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2),	112 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2, 113 maybePCRead, maybePCWrite), 114 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2, 115 maybePCRead, maybePCWrite), 116 'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2), 117 'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2), 118 'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2), 119 'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2), --- 12 unchanged lines hidden (view full) --- 132 maybePCRead, maybePCWrite), 133 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2, 134 maybePCRead, maybePCWrite), 135 'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2), 136 'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2), 137 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2), 138 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2), 139 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2),
	140 'FpOp1P4': ('FloatReg', 'sf', '(op1 + 4)', 'IsFloating', 2), 141 'FpOp1P5': ('FloatReg', 'sf', '(op1 + 5)', 'IsFloating', 2), 142 'FpOp1P6': ('FloatReg', 'sf', '(op1 + 6)', 'IsFloating', 2), 143 'FpOp1P7': ('FloatReg', 'sf', '(op1 + 7)', 'IsFloating', 2), 144 'FpOp1S0P0': ('FloatReg', 'sf', '(op1 + step * 0 + 0)', 'IsFloating', 2), 145 'FpOp1S0P1': ('FloatReg', 'sf', '(op1 + step * 0 + 1)', 'IsFloating', 2), 146 'FpOp1S1P0': ('FloatReg', 'sf', '(op1 + step * 1 + 0)', 'IsFloating', 2), 147 'FpOp1S1P1': ('FloatReg', 'sf', '(op1 + step * 1 + 1)', 'IsFloating', 2), 148 'FpOp1S2P0': ('FloatReg', 'sf', '(op1 + step * 2 + 0)', 'IsFloating', 2), 149 'FpOp1S2P1': ('FloatReg', 'sf', '(op1 + step * 2 + 1)', 'IsFloating', 2), 150 'FpOp1S3P0': ('FloatReg', 'sf', '(op1 + step * 3 + 0)', 'IsFloating', 2), 151 'FpOp1S3P1': ('FloatReg', 'sf', '(op1 + step * 3 + 1)', 'IsFloating', 2),
127 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2), 128 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2, 129 maybePCRead, maybePCWrite), 130 'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2), 131 'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2), 132 'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2), 133 'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2), 134 'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2), --- 24 unchanged lines hidden (view full) --- 159 INTREG_ZERO : INTREG_CONDCODES''', None, 2), 160 161 #Register fields for microops 162 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite), 163 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, 164 maybePCRead, maybeIWPCWrite), 165 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2), 166 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite),	152 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2), 153 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2, 154 maybePCRead, maybePCWrite), 155 'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2), 156 'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2), 157 'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2), 158 'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2), 159 'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2), --- 24 unchanged lines hidden (view full) --- 184 INTREG_ZERO : INTREG_CONDCODES''', None, 2), 185 186 #Register fields for microops 187 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite), 188 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, 189 maybePCRead, maybeIWPCWrite), 190 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2), 191 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite),
	192 'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 2, maybePCRead, maybePCWrite),
167 168 #General Purpose Floating Point Reg Operands 169 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2), 170 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2), 171 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2), 172 173 #Memory Operand 174 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2), --- 18 unchanged lines hidden ---	193 194 #General Purpose Floating Point Reg Operands 195 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2), 196 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2), 197 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2), 198 199 #Memory Operand 200 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2), --- 18 unchanged lines hidden ---