| operands.isa (7410:1589cdca3c6e) | operands.isa (7422:feddb9077def) |
|---|---|
| 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 140 unchanged lines hidden (view full) --- 149 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 150 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite), 151 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite), 152 'R7': ('IntReg', 'uw', '7', 'IsInteger', 2), 153 'R0': ('IntReg', 'uw', '0', 'IsInteger', 2), 154 155 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2), 156 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2), | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 140 unchanged lines hidden (view full) --- 149 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 150 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite), 151 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite), 152 'R7': ('IntReg', 'uw', '7', 'IsInteger', 2), 153 'R0': ('IntReg', 'uw', '0', 'IsInteger', 2), 154 155 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2), 156 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2), |
| 157 'OptCondCodes': ('IntReg', 'uw', 158 '''(condCode == COND_AL || condCode == COND_UC) ? 159 INTREG_ZERO : INTREG_CONDCODES''', None, 2), |
|
| 157 158 #Register fields for microops 159 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite), 160 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, 161 maybePCRead, maybeIWPCWrite), 162 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2), 163 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite), 164 --- 25 unchanged lines hidden --- | 160 161 #Register fields for microops 162 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite), 163 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, 164 maybePCRead, maybeIWPCWrite), 165 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2), 166 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite), 167 --- 25 unchanged lines hidden --- |