Cross Reference: /gem5/src/arch/arm/isa/operands.isa

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operands.isa (7361:e18233acf0be)	operands.isa (7408:ee6949c5bb5b)
1// -- mode:c++ -- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 157 unchanged lines hidden (view full) --- 166 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2), 167 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2), 168 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2), 169 170 #Memory Operand 171 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2), 172 173 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1),	1// -- mode:c++ -- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 157 unchanged lines hidden (view full) --- 166 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2), 167 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2), 168 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2), 169 170 #Memory Operand 171 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2), 172 173 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1),
	174 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 2),
174 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2), 175 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2), 176 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2), 177 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2), 178 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2), 179 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2), 180 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2), 181 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 182 readNPC, writeNPC), 183 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 184 readNPC, forceNPC), 185 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 186 readNPC, writeIWNPC), 187}};	175 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2), 176 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2), 177 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2), 178 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2), 179 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2), 180 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2), 181 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2), 182 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 183 readNPC, writeNPC), 184 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 185 readNPC, forceNPC), 186 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, 187 readNPC, writeIWNPC), 188}};