operands.isa (7310:239ab4e0c7d4) | operands.isa (7327:fc5a645b3aaa) |
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1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 77 unchanged lines hidden (view full) --- 86 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)' 87 forceNPC = 'xc->setNextPC(%(final_val)s)' 88}}; 89 90def operands {{ 91 #Abstracted integer reg operands 92 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, 93 maybePCRead, maybePCWrite), | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 77 unchanged lines hidden (view full) --- 86 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)' 87 forceNPC = 'xc->setNextPC(%(final_val)s)' 88}}; 89 90def operands {{ 91 #Abstracted integer reg operands 92 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, 93 maybePCRead, maybePCWrite), |
94 'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2), 95 'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2), 96 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2), 97 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2), 98 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2), |
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94 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2, 95 maybePCRead, maybePCWrite), 96 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2, 97 maybePCRead, maybePCWrite), | 99 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2, 100 maybePCRead, maybePCWrite), 101 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2, 102 maybePCRead, maybePCWrite), |
103 'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2), 104 'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2), 105 'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2), 106 'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2), 107 'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 2), |
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98 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, 99 maybePCRead, maybeIWPCWrite), 100 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, 101 maybePCRead, maybeAIWPCWrite), 102 'SpMode': ('IntReg', 'uw', 103 'intRegInMode((OperatingMode)regMode, INTREG_SP)', 104 'IsInteger', 2), 105 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2), 106 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0, 107 maybeAlignedPCRead, maybePCWrite), 108 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, 109 maybePCRead, maybePCWrite), 110 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2, 111 maybePCRead, maybePCWrite), | 108 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, 109 maybePCRead, maybeIWPCWrite), 110 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, 111 maybePCRead, maybeAIWPCWrite), 112 'SpMode': ('IntReg', 'uw', 113 'intRegInMode((OperatingMode)regMode, INTREG_SP)', 114 'IsInteger', 2), 115 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2), 116 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0, 117 maybeAlignedPCRead, maybePCWrite), 118 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, 119 maybePCRead, maybePCWrite), 120 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2, 121 maybePCRead, maybePCWrite), |
122 'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2), 123 'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2), 124 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2), 125 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2), 126 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2), |
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112 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2), 113 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2, 114 maybePCRead, maybePCWrite), | 127 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2), 128 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2, 129 maybePCRead, maybePCWrite), |
130 'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2), 131 'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2), 132 'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2), 133 'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2), 134 'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2), |
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115 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2, 116 maybePCRead, maybePCWrite), 117 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2, 118 maybePCRead, maybePCWrite), 119 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2, 120 maybePCRead, maybePCWrite), 121 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2, 122 maybePCRead, maybePCWrite), --- 43 unchanged lines hidden --- | 135 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2, 136 maybePCRead, maybePCWrite), 137 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2, 138 maybePCRead, maybePCWrite), 139 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2, 140 maybePCRead, maybePCWrite), 141 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2, 142 maybePCRead, maybePCWrite), --- 43 unchanged lines hidden --- |