operands.isa (7303:6b70985664c8) operands.isa (7310:239ab4e0c7d4)
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 85 unchanged lines hidden (view full) ---

94 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
95 maybePCRead, maybePCWrite),
96 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
97 maybePCRead, maybePCWrite),
98 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
99 maybePCRead, maybeIWPCWrite),
100 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
101 maybePCRead, maybeAIWPCWrite),
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 85 unchanged lines hidden (view full) ---

94 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
95 maybePCRead, maybePCWrite),
96 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
97 maybePCRead, maybePCWrite),
98 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
99 maybePCRead, maybeIWPCWrite),
100 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
101 maybePCRead, maybeAIWPCWrite),
102 'SpMode': ('IntReg', 'uw',
103 'intRegInMode((OperatingMode)regMode, INTREG_SP)',
104 'IsInteger', 2),
102 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
103 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,
104 maybeAlignedPCRead, maybePCWrite),
105 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
106 maybePCRead, maybePCWrite),
107 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
108 maybePCRead, maybePCWrite),
109 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),

--- 53 unchanged lines hidden --- 		105 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
106 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,
107 maybeAlignedPCRead, maybePCWrite),
108 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
109 maybePCRead, maybePCWrite),
110 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
111 maybePCRead, maybePCWrite),
112 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),

--- 53 unchanged lines hidden ---