operands.isa (7289:59247abdd4e2) operands.isa (7303:6b70985664c8)
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 77 unchanged lines hidden (view full) ---

86 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
87 forceNPC = 'xc->setNextPC(%(final_val)s)'
88}};
89
90def operands {{
91 #Abstracted integer reg operands
92 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
93 maybePCRead, maybePCWrite),
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 77 unchanged lines hidden (view full) ---

86 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
87 forceNPC = 'xc->setNextPC(%(final_val)s)'
88}};
89
90def operands {{
91 #Abstracted integer reg operands
92 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
93 maybePCRead, maybePCWrite),
94 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
95 maybePCRead, maybePCWrite),
94 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
95 maybePCRead, maybePCWrite),
96 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
97 maybePCRead, maybeIWPCWrite),
98 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
99 maybePCRead, maybeAIWPCWrite),
100 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
101 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,

--- 59 unchanged lines hidden --- 		96 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
97 maybePCRead, maybePCWrite),
98 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
99 maybePCRead, maybeIWPCWrite),
100 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
101 maybePCRead, maybeAIWPCWrite),
102 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
103 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,

--- 59 unchanged lines hidden ---