operands.isa (7279:157b02cc0ba1) | operands.isa (7288:7da4b77c4d29) |
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1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 74 unchanged lines hidden (view full) --- 83 readNPC = 'xc->readNextPC() & ~PcModeMask' 84 writeNPC = 'setNextPC(xc, %(final_val)s)' 85 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)' 86 forceNPC = 'xc->setNextPC(%(final_val)s)' 87}}; 88 89def operands {{ 90 #Abstracted integer reg operands | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 74 unchanged lines hidden (view full) --- 83 readNPC = 'xc->readNextPC() & ~PcModeMask' 84 writeNPC = 'setNextPC(xc, %(final_val)s)' 85 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)' 86 forceNPC = 'xc->setNextPC(%(final_val)s)' 87}}; 88 89def operands {{ 90 #Abstracted integer reg operands |
91 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, | 91 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, |
92 maybePCRead, maybePCWrite), | 92 maybePCRead, maybePCWrite), |
93 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 0, | 93 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2, |
94 maybePCRead, maybePCWrite), | 94 maybePCRead, maybePCWrite), |
95 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, | 95 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, |
96 maybePCRead, maybeIWPCWrite), | 96 maybePCRead, maybeIWPCWrite), |
97 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0, | 97 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2, |
98 maybePCRead, maybeAIWPCWrite), | 98 maybePCRead, maybeAIWPCWrite), |
99 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 0), 100 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1, | 99 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2), 100 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0, |
101 maybeAlignedPCRead, maybePCWrite), 102 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, 103 maybePCRead, maybePCWrite), | 101 maybeAlignedPCRead, maybePCWrite), 102 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, 103 maybePCRead, maybePCWrite), |
104 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, | 104 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2, |
105 maybePCRead, maybePCWrite), | 105 maybePCRead, maybePCWrite), |
106 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 0), 107 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, | 106 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2), 107 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2, |
108 maybePCRead, maybePCWrite), | 108 maybePCRead, maybePCWrite), |
109 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4, | 109 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2, |
110 maybePCRead, maybePCWrite), | 110 maybePCRead, maybePCWrite), |
111 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, | 111 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2, |
112 maybePCRead, maybePCWrite), | 112 maybePCRead, maybePCWrite), |
113 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6, | 113 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2, |
114 maybePCRead, maybePCWrite), | 114 maybePCRead, maybePCWrite), |
115 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 7, | 115 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2, |
116 maybePCRead, maybePCWrite), | 116 maybePCRead, maybePCWrite), |
117 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 8, | 117 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 2, |
118 maybePCRead, maybePCWrite), | 118 maybePCRead, maybePCWrite), |
119 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 9, | 119 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 2, |
120 maybePCRead, maybePCWrite), 121 #General Purpose Integer Reg Operands | 120 maybePCRead, maybePCWrite), 121 #General Purpose Integer Reg Operands |
122 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), | 122 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 2, maybePCRead, maybePCWrite), |
123 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), | 123 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), |
124 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 125 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), 126 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), 127 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0), | 124 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite), 125 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite), 126 'R7': ('IntReg', 'uw', '7', 'IsInteger', 2), 127 'R0': ('IntReg', 'uw', '0', 'IsInteger', 2), |
128 | 128 |
129 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 130 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), | 129 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2), 130 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2), |
131 132 #Register fields for microops | 131 132 #Register fields for microops |
133 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), 134 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, | 133 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite), 134 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, |
135 maybePCRead, maybeIWPCWrite), | 135 maybePCRead, maybeIWPCWrite), |
136 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11), 137 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), | 136 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2), 137 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite), |
138 139 #General Purpose Floating Point Reg Operands | 138 139 #General Purpose Floating Point Reg Operands |
140 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), 141 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 142 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), | 140 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2), 141 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2), 142 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2), |
143 144 #Memory Operand | 143 144 #Memory Operand |
145 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), | 145 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2), |
146 | 146 |
147 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40), 148 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41), 149 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42), 150 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43), 151 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44), 152 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45), 153 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, | 147 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1), 148 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2), 149 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2), 150 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2), 151 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2), 152 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2), 153 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, |
154 readNPC, writeNPC), | 154 readNPC, writeNPC), |
155 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, | 155 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, |
156 readNPC, forceNPC), | 156 readNPC, forceNPC), |
157 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51, | 157 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2, |
158 readNPC, writeIWNPC), 159}}; | 158 readNPC, writeIWNPC), 159}}; |