operands.isa (7241:0a9f0db3e5d8) operands.isa (7260:4e15b9b23abe)
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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89def operands {{
90 #Abstracted integer reg operands
91 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
92 maybePCRead, maybePCWrite),
93 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
94 maybePCRead, maybeIWPCWrite),
95 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
96 maybePCRead, maybeAIWPCWrite),
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 80 unchanged lines hidden (view full) ---

89def operands {{
90 #Abstracted integer reg operands
91 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
92 maybePCRead, maybePCWrite),
93 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
94 maybePCRead, maybeIWPCWrite),
95 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
96 maybePCRead, maybeAIWPCWrite),
97 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 0),
97 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
98 maybeAlignedPCRead, maybePCWrite),
99 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
100 maybePCRead, maybePCWrite),
101 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
102 maybePCRead, maybePCWrite),
98 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
99 maybeAlignedPCRead, maybePCWrite),
100 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
101 maybePCRead, maybePCWrite),
102 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
103 maybePCRead, maybePCWrite),
104 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 0),
103 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
104 maybePCRead, maybePCWrite),
105 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4,
106 maybePCRead, maybePCWrite),
107 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
108 maybePCRead, maybePCWrite),
109 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6,
110 maybePCRead, maybePCWrite),

--- 49 unchanged lines hidden --- 		105 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
106 maybePCRead, maybePCWrite),
107 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 4,
108 maybePCRead, maybePCWrite),
109 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
110 maybePCRead, maybePCWrite),
111 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6,
112 maybePCRead, maybePCWrite),

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