| operands.isa (7186:d4fc47ea5775) | operands.isa (7207:82cfe1198d6f) |
|---|---|
| 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 115 unchanged lines hidden (view full) --- 124 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 125 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 126 127 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 128 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), 129 130 #Register fields for microops 131 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 115 unchanged lines hidden (view full) --- 124 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 125 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 126 127 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), 128 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), 129 130 #Register fields for microops 131 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), |
| 132 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, 133 maybePCRead, maybeIWPCWrite), |
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| 132 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11), 133 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), 134 135 #General Purpose Floating Point Reg Operands 136 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), 137 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 138 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), 139 --- 16 unchanged lines hidden --- | 134 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 11), 135 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), 136 137 #General Purpose Floating Point Reg Operands 138 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), 139 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 140 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), 141 --- 16 unchanged lines hidden --- |