operands.isa (7184:c22d466f650a) operands.isa (7186:d4fc47ea5775)
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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51 'df' : ('float', 64)
52}};
53
54let {{
55 maybePCRead = '''
56 ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
57 xc->%(func)s(this, %(op_idx)s))
58 '''
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 42 unchanged lines hidden (view full) ---

51 'df' : ('float', 64)
52}};
53
54let {{
55 maybePCRead = '''
56 ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
57 xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybeAlignedPCRead = '''
60 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) :
61 xc->%(func)s(this, %(op_idx)s))
62 '''
59 maybePCWrite = '''
60 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
61 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62 '''
63 maybeIWPCWrite = '''
64 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
65 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66 '''

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86 #Abstracted integer reg operands
87 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
88 maybePCRead, maybePCWrite),
89 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
90 maybePCRead, maybeIWPCWrite),
91 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
92 maybePCRead, maybeAIWPCWrite),
93 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
63 maybePCWrite = '''
64 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
65 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66 '''
67 maybeIWPCWrite = '''
68 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
69 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
70 '''

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90 #Abstracted integer reg operands
91 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
92 maybePCRead, maybePCWrite),
93 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
94 maybePCRead, maybeIWPCWrite),
95 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
96 maybePCRead, maybeAIWPCWrite),
97 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
94 maybePCRead, maybePCWrite),
98 maybeAlignedPCRead, maybePCWrite),
95 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
96 maybePCRead, maybePCWrite),
97 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
98 maybePCRead, maybePCWrite),
99 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
100 maybePCRead, maybePCWrite),
101 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
102 maybePCRead, maybePCWrite),

--- 49 unchanged lines hidden --- 		99 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
100 maybePCRead, maybePCWrite),
101 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
102 maybePCRead, maybePCWrite),
103 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
104 maybePCRead, maybePCWrite),
105 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
106 maybePCRead, maybePCWrite),

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