operands.isa (7173:a056f86a4be3) operands.isa (7184:c22d466f650a)
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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59 maybePCWrite = '''
60 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
61 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62 '''
63 maybeIWPCWrite = '''
64 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
65 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66 '''
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 50 unchanged lines hidden (view full) ---

59 maybePCWrite = '''
60 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
61 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62 '''
63 maybeIWPCWrite = '''
64 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
65 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66 '''
67 maybeAIWPCWrite = '''
68 if (%(reg_idx)s == PCReg) {
69 if (xc->readPC() & (ULL(1) << PcTBitShift)) {
70 setIWNextPC(xc, %(final_val)s);
71 } else {
72 setNextPC(xc, %(final_val)s);
73 }
74 } else {
75 xc->%(func)s(this, %(op_idx)s, %(final_val)s);
76 }
77 '''
67
68 readNPC = 'xc->readNextPC() & ~PcModeMask'
69 writeNPC = 'setNextPC(xc, %(final_val)s)'
70 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
71 forceNPC = 'xc->setNextPC(%(final_val)s)'
72}};
73
74def operands {{
75 #Abstracted integer reg operands
76 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
77 maybePCRead, maybePCWrite),
78 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
79 maybePCRead, maybeIWPCWrite),
80 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
78
79 readNPC = 'xc->readNextPC() & ~PcModeMask'
80 writeNPC = 'setNextPC(xc, %(final_val)s)'
81 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
82 forceNPC = 'xc->setNextPC(%(final_val)s)'
83}};
84
85def operands {{
86 #Abstracted integer reg operands
87 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
88 maybePCRead, maybePCWrite),
89 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
90 maybePCRead, maybeIWPCWrite),
91 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
81 maybePCRead, maybeIWPCWrite),
92 maybePCRead, maybeAIWPCWrite),
82 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
83 maybePCRead, maybePCWrite),
84 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
85 maybePCRead, maybePCWrite),
86 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
87 maybePCRead, maybePCWrite),
88 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
89 maybePCRead, maybePCWrite),

--- 51 unchanged lines hidden --- 		93 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
94 maybePCRead, maybePCWrite),
95 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
96 maybePCRead, maybePCWrite),
97 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
98 maybePCRead, maybePCWrite),
99 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
100 maybePCRead, maybePCWrite),

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