| operands.isa (7151:672a20bbd4ff) | operands.isa (7160:3f4333b1d4af) |
|---|---|
| 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 75 unchanged lines hidden (view full) --- 84 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, 85 maybePCRead, maybePCWrite), 86 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, 87 maybePCRead, maybePCWrite), 88 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, 89 maybePCRead, maybePCWrite), 90 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, 91 maybePCRead, maybePCWrite), | 1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 75 unchanged lines hidden (view full) --- 84 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2, 85 maybePCRead, maybePCWrite), 86 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3, 87 maybePCRead, maybePCWrite), 88 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4, 89 maybePCRead, maybePCWrite), 90 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5, 91 maybePCRead, maybePCWrite), |
| 92 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 6, 93 maybePCRead, maybePCWrite), 94 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 7, 95 maybePCRead, maybePCWrite), 96 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 8, 97 maybePCRead, maybePCWrite), 98 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 9, 99 maybePCRead, maybePCWrite), |
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| 92 #General Purpose Integer Reg Operands 93 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 94 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 95 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 96 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), 97 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), 98 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0), 99 --- 34 unchanged lines hidden --- | 100 #General Purpose Integer Reg Operands 101 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite), 102 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite), 103 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite), 104 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite), 105 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5), 106 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0), 107 --- 34 unchanged lines hidden --- |