operands.isa (7148:1f8d18f5fe5d) operands.isa (7151:672a20bbd4ff)
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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63 maybeIWPCWrite = '''
64 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
65 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66 '''
67
68 readNPC = 'xc->readNextPC() & ~PcModeMask'
69 writeNPC = 'setNextPC(xc, %(final_val)s)'
70 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 54 unchanged lines hidden (view full) ---

63 maybeIWPCWrite = '''
64 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
65 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66 '''
67
68 readNPC = 'xc->readNextPC() & ~PcModeMask'
69 writeNPC = 'setNextPC(xc, %(final_val)s)'
70 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
71 forceNPC = 'xc->setNextPC(%(final_val)s)'
71}};
72
73def operands {{
74 #Abstracted integer reg operands
75 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
76 maybePCRead, maybePCWrite),
77 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
78 maybePCRead, maybeIWPCWrite),

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120 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
121 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
122 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
123 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
124 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
125 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
126 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
127 readNPC, writeNPC),
72}};
73
74def operands {{
75 #Abstracted integer reg operands
76 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
77 maybePCRead, maybePCWrite),
78 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
79 maybePCRead, maybeIWPCWrite),

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121 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
122 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
123 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
124 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
125 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
126 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
127 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
128 readNPC, writeNPC),
129 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
130 readNPC, forceNPC),
128 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
129 readNPC, writeIWNPC),
130}};
131 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
132 readNPC, writeIWNPC),
133}};