operands.isa (7093:9832d4b070fc) operands.isa (7114:5975996bcf2a)
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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56 ((%(reg_idx)s == PCReg) ? ((xc->readPC() & ~PcModeMask) + 8) :
57 xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybePCWrite = '''
60 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
61 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62 '''
63
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 47 unchanged lines hidden (view full) ---

56 ((%(reg_idx)s == PCReg) ? ((xc->readPC() & ~PcModeMask) + 8) :
57 xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybePCWrite = '''
60 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
61 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62 '''
63
64 readPC = 'xc->readPC() & ~PcModeMask'
65 writePC = 'setPC(xc, %(final_val)s)'
66
64 readNPC = 'xc->readNextPC() & ~PcModeMask'
65 writeNPC = 'setNextPC(xc, %(final_val)s)'
66}};
67
68def operands {{
69 #General Purpose Integer Reg Operands
70 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
71 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),

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96 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
97
98 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
99 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
100 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
101 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
102 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
103 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
67 readNPC = 'xc->readNextPC() & ~PcModeMask'
68 writeNPC = 'setNextPC(xc, %(final_val)s)'
69}};
70
71def operands {{
72 #General Purpose Integer Reg Operands
73 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
74 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),

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99 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
100
101 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
102 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
103 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
104 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
105 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
106 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
104 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 50,
107 'PC': ('PC', 'ud', None, (None, None, 'IsControl'), 50,
108 readPC, writePC),
109 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
105 readNPC, writeNPC),
106}};
110 readNPC, writeNPC),
111}};