operands.isa (7091:050e5e2aa89f) operands.isa (7093:9832d4b070fc)
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

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48 'uw' : ('unsigned int', 32),
49 'ud' : ('unsigned int', 64),
50 'sf' : ('float', 32),
51 'df' : ('float', 64)
52}};
53
54let {{
55 maybePCRead = '''
1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 39 unchanged lines hidden (view full) ---

48 'uw' : ('unsigned int', 32),
49 'ud' : ('unsigned int', 64),
50 'sf' : ('float', 32),
51 'df' : ('float', 64)
52}};
53
54let {{
55 maybePCRead = '''
56 ((%(reg_idx)s == PCReg) ? (xc->readPC() + 8) :
56 ((%(reg_idx)s == PCReg) ? ((xc->readPC() & ~PcModeMask) + 8) :
57 xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybePCWrite = '''
57 xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybePCWrite = '''
60 ((%(reg_idx)s == PCReg) ? xc->setNextPC(%(final_val)s) :
60 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
61 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62 '''
61 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62 '''
63
64 readNPC = 'xc->readNextPC() & ~PcModeMask'
65 writeNPC = 'setNextPC(xc, %(final_val)s)'
63}};
64
65def operands {{
66 #General Purpose Integer Reg Operands
67 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
68 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
69 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
70 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),

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87 #General Purpose Floating Point Reg Operands
88 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
89 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
90 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
91
92 #Memory Operand
93 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
94
66}};
67
68def operands {{
69 #General Purpose Integer Reg Operands
70 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
71 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
72 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
73 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),

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90 #General Purpose Floating Point Reg Operands
91 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
92 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
93 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
94
95 #Memory Operand
96 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
97
95 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', None, 40),
98 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
96 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
97 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
98 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
99 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
100 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
99 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
100 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
101 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
102 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
103 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
101 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 50),
102 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 51)
103
104 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 50,
105 readNPC, writeNPC),
104}};
106}};