operands.isa (6746:7d2767d7896f) | operands.isa (7091:050e5e2aa89f) |
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1// -*- mode:c++ -*- | 1// -*- mode:c++ -*- |
2 | 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software 9// licensed hereunder. You may use the software subject to the license 10// terms below provided that you ensure that this notice is replicated 11// unmodified and in its entirety in all distributions of the software, 12// modified or unmodified, in source code or in binary form. 13// |
3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright 9// notice, this list of conditions and the following disclaimer; 10// redistributions in binary form must reproduce the above copyright --- 51 unchanged lines hidden (view full) --- 62 63 #Destination register for load/store double instructions 64 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 65 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 66 67 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7), 68 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8), 69 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), | 14// Copyright (c) 2007-2008 The Florida State University 15// All rights reserved. 16// 17// Redistribution and use in source and binary forms, with or without 18// modification, are permitted provided that the following conditions are 19// met: redistributions of source code must retain the above copyright 20// notice, this list of conditions and the following disclaimer; 21// redistributions in binary form must reproduce the above copyright --- 51 unchanged lines hidden (view full) --- 73 74 #Destination register for load/store double instructions 75 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite), 76 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite), 77 78 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7), 79 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8), 80 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9), |
70 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', 'IsInteger', 10), | 81 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10), |
71 72 #Register fields for microops 73 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), 74 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), 75 76 #General Purpose Floating Point Reg Operands 77 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), 78 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 79 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), 80 81 #Memory Operand 82 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), 83 | 82 83 #Register fields for microops 84 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite), 85 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite), 86 87 #General Purpose Floating Point Reg Operands 88 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20), 89 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 90 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), 91 92 #Memory Operand 93 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), 94 |
84 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40), 85 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', (None, None, 'IsControl'), 41), 86 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', (None, None, 'IsControl'), 42), 87 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', (None, None, 'IsControl'), 43), 88 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', (None, None, 'IsControl'), 44), 89 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', (None, None, 'IsControl'), 45), | 95 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', None, 40), 96 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41), 97 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42), 98 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43), 99 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44), 100 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45), |
90 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 50), 91 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 51) 92 93}}; | 101 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 50), 102 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 51) 103 104}}; |