operands.isa (6741:73d89772f409) operands.isa (6745:cdc62b81747e)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 68 unchanged lines hidden (view full) ---

77 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
78 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
79 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
80
81 #Memory Operand
82 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
83
84 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 68 unchanged lines hidden (view full) ---

77 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
78 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
79 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
80
81 #Memory Operand
82 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
83
84 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
85 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
86 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 42),
87 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 43),
88 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 44),
89 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 45),
90 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 46)
85 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', 'IsInteger', 41),
86 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 42),
87 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 43),
88 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 44),
89 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 45),
90 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 50),
91 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 51)
91
92}};
92
93}};