operands.isa (6724:70129fdded75) operands.isa (6741:73d89772f409)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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53
54def operands {{
55 #General Purpose Integer Reg Operands
56 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
57 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
58 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
59 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
60 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 44 unchanged lines hidden (view full) ---

53
54def operands {{
55 #General Purpose Integer Reg Operands
56 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
57 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
58 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
59 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
60 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
61 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
61
62 #Destination register for load/store double instructions
63 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
64 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
65
66 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
67 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
68 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),

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63 #Destination register for load/store double instructions
64 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
65 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
66
67 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
68 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
69 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),

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