operands.isa (6720:36aa46630e62) operands.isa (6721:77318ac91316)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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58 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
59 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
60 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
61
62 #Destination register for load/store double instructions
63 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
64 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
65
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 49 unchanged lines hidden (view full) ---

58 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
59 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
60 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
61
62 #Destination register for load/store double instructions
63 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
64 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
65
66 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7),
67 'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8),
68 'LR': ('IntReg', 'uw', '14', 'IsInteger', 9),
66 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
67 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
68 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
69
70 #Register fields for microops
71 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
72 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
73
74 #General Purpose Floating Point Reg Operands
75 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
76 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),

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70 #Register fields for microops
71 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
72 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
73
74 #General Purpose Floating Point Reg Operands
75 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
76 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),

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