operands.isa (6393:1895318a1b26) | operands.isa (6403:c3372644e033) |
---|---|
1// -*- mode:c++ -*- 2 3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 68 unchanged lines hidden (view full) --- 77 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 78 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), 79 80 #Memory Operand 81 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), 82 83 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40), 84 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41), | 1// -*- mode:c++ -*- 2 3// Copyright (c) 2007-2008 The Florida State University 4// All rights reserved. 5// 6// Redistribution and use in source and binary forms, with or without 7// modification, are permitted provided that the following conditions are 8// met: redistributions of source code must retain the above copyright --- 68 unchanged lines hidden (view full) --- 77 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21), 78 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22), 79 80 #Memory Operand 81 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30), 82 83 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40), 84 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41), |
85 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42), 86 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43), | 85 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', 'IsInteger', 42), 86 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', 'IsInteger', 43), 87 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', 'IsInteger', 44), 88 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 45), 89 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 46) |
87 88}}; | 90 91}}; |