operands.isa (6299:e61df5581723) operands.isa (6308:46fcf4dc4c30)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 42 unchanged lines hidden (view full) ---

51 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4),
52 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5),
53
54 'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 6),
55 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7),
56 'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8),
57 'LR': ('IntReg', 'uw', '14', 'IsInteger', 9),
58
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 42 unchanged lines hidden (view full) ---

51 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4),
52 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5),
53
54 'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 6),
55 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7),
56 'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8),
57 'LR': ('IntReg', 'uw', '14', 'IsInteger', 9),
58
59 #Register fields for microops
60 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11),
61 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12),
62
59 #General Purpose Floating Point Reg Operands
60 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
61 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
62 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
63
64 #Memory Operand
65 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
66
67 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
68 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
69 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42),
70 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43),
71
72}};
63 #General Purpose Floating Point Reg Operands
64 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
65 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
66 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
67
68 #Memory Operand
69 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
70
71 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
72 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
73 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42),
74 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43),
75
76}};