operands.isa (6248:75adb07279b4) operands.isa (6299:e61df5581723)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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42
43def operands {{
44 #General Purpose Integer Reg Operands
45 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
46 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2),
47 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
48 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
49
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 33 unchanged lines hidden (view full) ---

42
43def operands {{
44 #General Purpose Integer Reg Operands
45 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1),
46 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2),
47 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
48 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4),
49
50 'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 5),
51 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 5),
52 'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 6),
53 'LR': ('IntReg', 'uw', '14', 'IsInteger', 6),
50 #Destination register for load/store double instructions
51 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4),
52 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5),
54
53
54 'Raddr': ('IntReg', 'uw', '17', 'IsInteger', 6),
55 'Rhi': ('IntReg', 'uw', '18', 'IsInteger', 7),
56 'Rlo': ('IntReg', 'uw', '19', 'IsInteger', 8),
57 'LR': ('IntReg', 'uw', '14', 'IsInteger', 9),
58
55 #General Purpose Floating Point Reg Operands
59 #General Purpose Floating Point Reg Operands
56 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
57 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
58 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3),
60 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
61 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
62 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
59
60 #Memory Operand
63
64 #Memory Operand
61 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
65 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
62
66
63 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 7),
64 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 7),
65 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9),
66 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 9),
67 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 40),
68 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 41),
69 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 42),
70 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 43),
67
68}};
71
72}};