operands.isa (6019:76890d8b28f5) operands.isa (6242:1cee707c1228)
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

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59 #General Purpose Floating Point Reg Operands
60 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
61 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
62 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3),
63
64 #Memory Operand
65 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
66
1// -*- mode:c++ -*-
2
3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright

--- 50 unchanged lines hidden (view full) ---

59 #General Purpose Floating Point Reg Operands
60 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 1),
61 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
62 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3),
63
64 #Memory Operand
65 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 8),
66
67 'Cpsr': ('ControlReg', 'uw', 'CPSR', 'IsInteger', 7),
68 'Fpsr': ('ControlReg', 'uw', 'FPSR', 'IsInteger', 7),
67 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', 'IsInteger', 7),
68 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', 'IsInteger', 7),
69 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9),
70 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 9),
71
72}};
69 'NPC': ('NPC', 'uw', None, (None, None, 'IsControl'), 9),
70 'NNPC': ('NNPC', 'uw', None, (None, None, 'IsControl'), 9),
71
72}};