| operands.isa (14028:44edf7dbe672) | operands.isa (14091:090449e74135) |
|---|---|
| 1// -*- mode:c++ -*- 2// Copyright (c) 2010-2014, 2016-2018 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 567 unchanged lines hidden (view full) --- 576 577 # Predicate register operands 578 'GpOp': vecPredReg('gp'), 579 'POp1': vecPredReg('op1'), 580 'POp2': vecPredReg('op2'), 581 'PDest': vecPredReg('dest'), 582 'PDestMerge': vecPredReg('dest'), 583 'Ffr': vecPredReg('PREDREG_FFR'), | 1// -*- mode:c++ -*- 2// Copyright (c) 2010-2014, 2016-2018 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 567 unchanged lines hidden (view full) --- 576 577 # Predicate register operands 578 'GpOp': vecPredReg('gp'), 579 'POp1': vecPredReg('op1'), 580 'POp2': vecPredReg('op2'), 581 'PDest': vecPredReg('dest'), 582 'PDestMerge': vecPredReg('dest'), 583 'Ffr': vecPredReg('PREDREG_FFR'), |
| 584 'FfrAux': vecPredReg('PREDREG_FFR'), 585 'PUreg0': vecPredReg('PREDREG_UREG0'), |
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| 584 585 #Abstracted control reg operands 586 'MiscDest': cntrlReg('dest'), 587 'MiscOp1': cntrlReg('op1'), 588 'MiscNsBankedDest': cntrlNsBankedReg('dest'), 589 'MiscNsBankedOp1': cntrlNsBankedReg('op1'), 590 'MiscNsBankedDest64': cntrlNsBankedReg64('dest'), 591 'MiscNsBankedOp164': cntrlNsBankedReg64('op1'), --- 65 unchanged lines hidden --- | 586 587 #Abstracted control reg operands 588 'MiscDest': cntrlReg('dest'), 589 'MiscOp1': cntrlReg('op1'), 590 'MiscNsBankedDest': cntrlNsBankedReg('dest'), 591 'MiscNsBankedOp1': cntrlNsBankedReg('op1'), 592 'MiscNsBankedDest64': cntrlNsBankedReg64('dest'), 593 'MiscNsBankedOp164': cntrlNsBankedReg64('op1'), --- 65 unchanged lines hidden --- |