| operands.isa (13596:5a0cd4c66ca0) | operands.isa (13603:203e36327db9) |
|---|---|
| 1// -*- mode:c++ -*- 2// Copyright (c) 2010-2014, 2016 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 246 unchanged lines hidden (view full) --- 255 'OptCondCodesV': ccReg( 256 '''((condCode == COND_VS || condCode == COND_VC || 257 condCode == COND_GE || condCode == COND_LT || 258 condCode == COND_GT || condCode == COND_LE) ? 259 CCREG_V : CCREG_ZERO)'''), 260 'FpCondCodes': ccReg('CCREG_FP'), 261 262 #Abstracted floating point reg operands | 1// -*- mode:c++ -*- 2// Copyright (c) 2010-2014, 2016 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 246 unchanged lines hidden (view full) --- 255 'OptCondCodesV': ccReg( 256 '''((condCode == COND_VS || condCode == COND_VC || 257 condCode == COND_GE || condCode == COND_LT || 258 condCode == COND_GT || condCode == COND_LE) ? 259 CCREG_V : CCREG_ZERO)'''), 260 'FpCondCodes': ccReg('CCREG_FP'), 261 262 #Abstracted floating point reg operands |
| 263 'FpDest': floatReg('(dest + 0)'), 264 'FpDestP0': floatReg('(dest + 0)'), 265 'FpDestP1': floatReg('(dest + 1)'), 266 'FpDestP2': floatReg('(dest + 2)'), 267 'FpDestP3': floatReg('(dest + 3)'), 268 'FpDestP4': floatReg('(dest + 4)'), 269 'FpDestP5': floatReg('(dest + 5)'), 270 'FpDestP6': floatReg('(dest + 6)'), 271 'FpDestP7': floatReg('(dest + 7)'), 272 'FpDestS0P0': floatReg('(dest + step * 0 + 0)'), 273 'FpDestS0P1': floatReg('(dest + step * 0 + 1)'), 274 'FpDestS1P0': floatReg('(dest + step * 1 + 0)'), 275 'FpDestS1P1': floatReg('(dest + step * 1 + 1)'), 276 'FpDestS2P0': floatReg('(dest + step * 2 + 0)'), 277 'FpDestS2P1': floatReg('(dest + step * 2 + 1)'), 278 'FpDestS3P0': floatReg('(dest + step * 3 + 0)'), 279 'FpDestS3P1': floatReg('(dest + step * 3 + 1)'), | 263 'FpDest': vectorElem('dest / 4', 'dest % 4'), 264 'FpDestP0': vectorElem('dest / 4', '(dest % 4) + 0'), 265 'FpDestP1': vectorElem('dest / 4', '(dest % 4) + 1'), 266 'FpDestP2': vectorElem('dest / 4', '(dest % 4) + 2'), 267 'FpDestP3': vectorElem('dest / 4', '(dest % 4) + 3'), 268 'FpDestP4': vectorElem('(dest / 4) + 1', '(dest % 4) + 0'), 269 'FpDestP5': vectorElem('(dest / 4) + 1', '(dest % 4) + 1'), 270 'FpDestP6': vectorElem('(dest / 4) + 1', '(dest % 4) + 2'), 271 'FpDestP7': vectorElem('(dest / 4) + 1', '(dest % 4) + 3'), |
| 280 | 272 |
| 281 'FpDest2': floatReg('(dest2 + 0)'), 282 'FpDest2P0': floatReg('(dest2 + 0)'), 283 'FpDest2P1': floatReg('(dest2 + 1)'), 284 'FpDest2P2': floatReg('(dest2 + 2)'), 285 'FpDest2P3': floatReg('(dest2 + 3)'), | 273 'FpDestS0P0': vectorElem( 274 '(dest + step * 0 + 0) / 4', '(dest + step * 0 + 0) % 4'), 275 'FpDestS0P1': vectorElem( 276 '(dest + step * 0 + 1) / 4', '(dest + step * 0 + 1) % 4'), 277 'FpDestS1P0': vectorElem( 278 '(dest + step * 1 + 0) / 4', '(dest + step * 1 + 0) % 4'), 279 'FpDestS1P1': vectorElem( 280 '(dest + step * 1 + 1) / 4', '(dest + step * 1 + 1) % 4'), 281 'FpDestS2P0': vectorElem( 282 '(dest + step * 2 + 0) / 4', '(dest + step * 2 + 0) % 4'), 283 'FpDestS2P1': vectorElem( 284 '(dest + step * 2 + 1) / 4', '(dest + step * 2 + 1) % 4'), 285 'FpDestS3P0': vectorElem( 286 '(dest + step * 3 + 0) / 4', '(dest + step * 3 + 0) % 4'), 287 'FpDestS3P1': vectorElem( 288 '(dest + step * 3 + 1) / 4', '(dest + step * 3 + 1) % 4'), |
| 286 | 289 |
| 287 'FpOp1': floatReg('(op1 + 0)'), 288 'FpOp1P0': floatReg('(op1 + 0)'), 289 'FpOp1P1': floatReg('(op1 + 1)'), 290 'FpOp1P2': floatReg('(op1 + 2)'), 291 'FpOp1P3': floatReg('(op1 + 3)'), 292 'FpOp1P4': floatReg('(op1 + 4)'), 293 'FpOp1P5': floatReg('(op1 + 5)'), 294 'FpOp1P6': floatReg('(op1 + 6)'), 295 'FpOp1P7': floatReg('(op1 + 7)'), 296 'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'), 297 'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'), 298 'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'), 299 'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'), 300 'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'), 301 'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'), 302 'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'), 303 'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'), | 290 'FpDest2': vectorElem('dest2 / 4', 'dest2 % 4'), 291 'FpDest2P0': vectorElem('dest2 / 4', '(dest2 % 4) + 0'), 292 'FpDest2P1': vectorElem('dest2 / 4', '(dest2 % 4) + 1'), 293 'FpDest2P2': vectorElem('dest2 / 4', '(dest2 % 4) + 2'), 294 'FpDest2P3': vectorElem('dest2 / 4', '(dest2 % 4) + 3'), |
| 304 | 295 |
| 305 'FpOp2': floatReg('(op2 + 0)'), 306 'FpOp2P0': floatReg('(op2 + 0)'), 307 'FpOp2P1': floatReg('(op2 + 1)'), 308 'FpOp2P2': floatReg('(op2 + 2)'), 309 'FpOp2P3': floatReg('(op2 + 3)'), | 296 'FpOp1': vectorElem('op1 / 4', 'op1 % 4'), 297 'FpOp1P0': vectorElem('op1 / 4', '(op1 % 4) + 0'), 298 'FpOp1P1': vectorElem('op1 / 4', '(op1 % 4) + 1'), 299 'FpOp1P2': vectorElem('op1 / 4', '(op1 % 4) + 2'), 300 'FpOp1P3': vectorElem('op1 / 4', '(op1 % 4) + 3'), 301 'FpOp1P4': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 0'), 302 'FpOp1P5': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 1'), 303 'FpOp1P6': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 2'), 304 'FpOp1P7': vectorElem('(op1 / 4) + 1', '(op1 % 4) + 3'), |
| 310 | 305 |
| 306 'FpOp1S0P0': vectorElem( 307 '(op1 + step * 0 + 0) / 4', '(op1 + step * 0 + 0) % 4'), 308 'FpOp1S0P1': vectorElem( 309 '(op1 + step * 0 + 1) / 4', '(op1 + step * 0 + 1) % 4'), 310 'FpOp1S1P0': vectorElem( 311 '(op1 + step * 1 + 0) / 4', '(op1 + step * 1 + 0) % 4'), 312 'FpOp1S1P1': vectorElem( 313 '(op1 + step * 1 + 1) / 4', '(op1 + step * 1 + 1) % 4'), 314 'FpOp1S2P0': vectorElem( 315 '(op1 + step * 2 + 0) / 4', '(op1 + step * 2 + 0) % 4'), 316 'FpOp1S2P1': vectorElem( 317 '(op1 + step * 2 + 1) / 4', '(op1 + step * 2 + 1) % 4'), 318 'FpOp1S3P0': vectorElem( 319 '(op1 + step * 3 + 0) / 4', '(op1 + step * 3 + 0) % 4'), 320 'FpOp1S3P1': vectorElem( 321 '(op1 + step * 3 + 1) / 4', '(op1 + step * 3 + 1) % 4'), 322 323 'FpOp2': vectorElem('op2 / 4', 'op2 % 4'), 324 'FpOp2P0': vectorElem('op2 / 4', '(op2 % 4) + 0'), 325 'FpOp2P1': vectorElem('op2 / 4', '(op2 % 4) + 1'), 326 'FpOp2P2': vectorElem('op2 / 4', '(op2 % 4) + 2'), 327 'FpOp2P3': vectorElem('op2 / 4', '(op2 % 4) + 3'), 328 |
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| 311 # Create AArch64 unpacked view of the FP registers 312 # Name ::= 'AA64Vec' OpSpec [LaneSpec] 313 # OpSpec ::= IOSpec [Index] [Plus] 314 # IOSpec ::= 'S' | 'D' 315 # Index ::= '0' | ... | '9' 316 # Plus ::= [PlusAmount] ['l'] 317 # PlusAmount ::= 'p' [PlusAmount] 318 # LaneSpec ::= 'L' Index --- 224 unchanged lines hidden (view full) --- 543 'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'), 544 'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'), 545 546 #Register fields for microops 547 'URa' : intReg('ura'), 548 'XURa' : intRegX64('ura'), 549 'WURa' : intRegW64('ura'), 550 'IWRa' : intRegIWPC('ura'), | 329 # Create AArch64 unpacked view of the FP registers 330 # Name ::= 'AA64Vec' OpSpec [LaneSpec] 331 # OpSpec ::= IOSpec [Index] [Plus] 332 # IOSpec ::= 'S' | 'D' 333 # Index ::= '0' | ... | '9' 334 # Plus ::= [PlusAmount] ['l'] 335 # PlusAmount ::= 'p' [PlusAmount] 336 # LaneSpec ::= 'L' Index --- 224 unchanged lines hidden (view full) --- 561 'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'), 562 'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'), 563 564 #Register fields for microops 565 'URa' : intReg('ura'), 566 'XURa' : intRegX64('ura'), 567 'WURa' : intRegW64('ura'), 568 'IWRa' : intRegIWPC('ura'), |
| 551 'Fa' : floatReg('ura'), | 569 'Fa' : vectorElem('ura / 4', 'ura % 4'), |
| 552 'URb' : intReg('urb'), 553 'XURb' : intRegX64('urb'), 554 'URc' : intReg('urc'), 555 'XURc' : intRegX64('urc'), 556 557 #Memory Operand 558 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal), 559 --- 22 unchanged lines hidden --- | 570 'URb' : intReg('urb'), 571 'XURb' : intRegX64('urb'), 572 'URc' : intReg('urc'), 573 'XURc' : intRegX64('urc'), 574 575 #Memory Operand 576 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal), 577 --- 22 unchanged lines hidden --- |