| operands.isa (12499:b81688796004) | operands.isa (13596:5a0cd4c66ca0) |
|---|---|
| 1// -*- mode:c++ -*- 2// Copyright (c) 2010-2014, 2016 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 178 unchanged lines hidden (view full) --- 187 'Dest': intReg('dest'), 188 'Dest64': intReg64('dest'), 189 'XDest': intRegX64('dest'), 190 'WDest': intRegW64('dest'), 191 'IWDest': intRegIWPC('dest'), 192 'AIWDest': intRegAIWPC('dest'), 193 'Dest2': intReg('dest2'), 194 'XDest2': intRegX64('dest2'), | 1// -*- mode:c++ -*- 2// Copyright (c) 2010-2014, 2016 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 178 unchanged lines hidden (view full) --- 187 'Dest': intReg('dest'), 188 'Dest64': intReg64('dest'), 189 'XDest': intRegX64('dest'), 190 'WDest': intRegW64('dest'), 191 'IWDest': intRegIWPC('dest'), 192 'AIWDest': intRegAIWPC('dest'), 193 'Dest2': intReg('dest2'), 194 'XDest2': intRegX64('dest2'), |
| 195 'FDest2': floatReg('dest2'), | |
| 196 'IWDest2': intRegIWPC('dest2'), 197 'Result': intReg('result'), 198 'XResult': intRegX64('result'), 199 'XBase': intRegX64('base', id = srtBase), 200 'Base': intRegAPC('base', id = srtBase), 201 'XOffset': intRegX64('offset'), 202 'Index': intReg('index'), 203 'Shift': intReg('shift'), --- 341 unchanged lines hidden (view full) --- 545 'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'), 546 547 #Register fields for microops 548 'URa' : intReg('ura'), 549 'XURa' : intRegX64('ura'), 550 'WURa' : intRegW64('ura'), 551 'IWRa' : intRegIWPC('ura'), 552 'Fa' : floatReg('ura'), | 195 'IWDest2': intRegIWPC('dest2'), 196 'Result': intReg('result'), 197 'XResult': intRegX64('result'), 198 'XBase': intRegX64('base', id = srtBase), 199 'Base': intRegAPC('base', id = srtBase), 200 'XOffset': intRegX64('offset'), 201 'Index': intReg('index'), 202 'Shift': intReg('shift'), --- 341 unchanged lines hidden (view full) --- 544 'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'), 545 546 #Register fields for microops 547 'URa' : intReg('ura'), 548 'XURa' : intRegX64('ura'), 549 'WURa' : intRegW64('ura'), 550 'IWRa' : intRegIWPC('ura'), 551 'Fa' : floatReg('ura'), |
| 553 'FaP1' : floatReg('ura + 1'), | |
| 554 'URb' : intReg('urb'), 555 'XURb' : intRegX64('urb'), 556 'URc' : intReg('urc'), 557 'XURc' : intRegX64('urc'), 558 559 #Memory Operand 560 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal), 561 --- 22 unchanged lines hidden --- | 552 'URb' : intReg('urb'), 553 'XURb' : intRegX64('urb'), 554 'URc' : intReg('urc'), 555 'XURc' : intRegX64('urc'), 556 557 #Memory Operand 558 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal), 559 --- 22 unchanged lines hidden --- |