operands.isa (12110:c24ee249b8ba) operands.isa (12134:604f47f63877)
1// -*- mode:c++ -*-
2// Copyright (c) 2010-2014, 2016 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 179 unchanged lines hidden (view full) ---

188 'Dest64': intReg64('dest'),
189 'XDest': intRegX64('dest'),
190 'WDest': intRegW64('dest'),
191 'IWDest': intRegIWPC('dest'),
192 'AIWDest': intRegAIWPC('dest'),
193 'Dest2': intReg('dest2'),
194 'XDest2': intRegX64('dest2'),
195 'FDest2': floatReg('dest2'),
1// -*- mode:c++ -*-
2// Copyright (c) 2010-2014, 2016 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software

--- 179 unchanged lines hidden (view full) ---

188 'Dest64': intReg64('dest'),
189 'XDest': intRegX64('dest'),
190 'WDest': intRegW64('dest'),
191 'IWDest': intRegIWPC('dest'),
192 'AIWDest': intRegAIWPC('dest'),
193 'Dest2': intReg('dest2'),
194 'XDest2': intRegX64('dest2'),
195 'FDest2': floatReg('dest2'),
196 'IWDest2': intRegIWPC('dest2'),
196 'Result': intReg('result'),
197 'XResult': intRegX64('result'),
198 'XBase': intRegX64('base', id = srtBase),
199 'Base': intRegAPC('base', id = srtBase),
200 'XOffset': intRegX64('offset'),
201 'Index': intReg('index'),
202 'Shift': intReg('shift'),
203 'Op1': intReg('op1'),

--- 379 unchanged lines hidden --- 		197 'Result': intReg('result'),
198 'XResult': intRegX64('result'),
199 'XBase': intRegX64('base', id = srtBase),
200 'Base': intRegAPC('base', id = srtBase),
201 'XOffset': intRegX64('offset'),
202 'Index': intReg('index'),
203 'Shift': intReg('shift'),
204 'Op1': intReg('op1'),

--- 379 unchanged lines hidden ---