operands.isa (11514:eb53b59ea625) operands.isa (12110:c24ee249b8ba)
1// -*- mode:c++ -*-
1// -*- mode:c++ -*-
2// Copyright (c) 2010-2014 ARM Limited
2// Copyright (c) 2010-2014, 2016 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated

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44 'ub' : 'uint8_t',
45 'sh' : 'int16_t',
46 'uh' : 'uint16_t',
47 'sw' : 'int32_t',
48 'uw' : 'uint32_t',
49 'ud' : 'uint64_t',
50 'tud' : 'Twin64_t',
51 'sf' : 'float',
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated

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44 'ub' : 'uint8_t',
45 'sh' : 'int16_t',
46 'uh' : 'uint16_t',
47 'sw' : 'int32_t',
48 'uw' : 'uint32_t',
49 'ud' : 'uint64_t',
50 'tud' : 'Twin64_t',
51 'sf' : 'float',
52 'df' : 'double'
52 'df' : 'double',
53 'vc' : 'TheISA::VecRegContainer',
54 # For operations that are implemented as a template
55 'x' : 'TPElem',
53}};
54
55let {{
56 maybePCRead = '''
57 ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybeAlignedPCRead = '''
60 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :

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112 #R15, the updates are layered properly and the R15 update isn't lost.
113 srtNormal = 5
114 srtCpsr = 4
115 srtBase = 3
116 srtPC = 2
117 srtMode = 1
118 srtEPC = 0
119
56}};
57
58let {{
59 maybePCRead = '''
60 ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
61 '''
62 maybeAlignedPCRead = '''
63 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :

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115 #R15, the updates are layered properly and the R15 update isn't lost.
116 srtNormal = 5
117 srtCpsr = 4
118 srtBase = 3
119 srtPC = 2
120 srtMode = 1
121 srtEPC = 0
122
123 def vectorElem(idx, elem):
124 return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)
125
126 def vectorReg(idx, elems = None):
127 return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
128
129 def vectorRegElem(elem, ext = 'sf', zeroing = False):
130 return (elem, ext, zeroing)
131
120 def floatReg(idx):
121 return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
122
123 def intReg(idx):
124 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
125 maybePCRead, maybePCWrite)
126
127 def intReg64(idx):

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292
293 'FpOp2': floatReg('(op2 + 0)'),
294 'FpOp2P0': floatReg('(op2 + 0)'),
295 'FpOp2P1': floatReg('(op2 + 1)'),
296 'FpOp2P2': floatReg('(op2 + 2)'),
297 'FpOp2P3': floatReg('(op2 + 3)'),
298
299 # Create AArch64 unpacked view of the FP registers
132 def floatReg(idx):
133 return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
134
135 def intReg(idx):
136 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
137 maybePCRead, maybePCWrite)
138
139 def intReg64(idx):

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304
305 'FpOp2': floatReg('(op2 + 0)'),
306 'FpOp2P0': floatReg('(op2 + 0)'),
307 'FpOp2P1': floatReg('(op2 + 1)'),
308 'FpOp2P2': floatReg('(op2 + 2)'),
309 'FpOp2P3': floatReg('(op2 + 3)'),
310
311 # Create AArch64 unpacked view of the FP registers
300 'AA64FpOp1P0': floatReg('((op1 * 4) + 0)'),
301 'AA64FpOp1P1': floatReg('((op1 * 4) + 1)'),
302 'AA64FpOp1P2': floatReg('((op1 * 4) + 2)'),
303 'AA64FpOp1P3': floatReg('((op1 * 4) + 3)'),
304 'AA64FpOp2P0': floatReg('((op2 * 4) + 0)'),
305 'AA64FpOp2P1': floatReg('((op2 * 4) + 1)'),
306 'AA64FpOp2P2': floatReg('((op2 * 4) + 2)'),
307 'AA64FpOp2P3': floatReg('((op2 * 4) + 3)'),
308 'AA64FpOp3P0': floatReg('((op3 * 4) + 0)'),
309 'AA64FpOp3P1': floatReg('((op3 * 4) + 1)'),
310 'AA64FpOp3P2': floatReg('((op3 * 4) + 2)'),
311 'AA64FpOp3P3': floatReg('((op3 * 4) + 3)'),
312 'AA64FpDestP0': floatReg('((dest * 4) + 0)'),
313 'AA64FpDestP1': floatReg('((dest * 4) + 1)'),
314 'AA64FpDestP2': floatReg('((dest * 4) + 2)'),
315 'AA64FpDestP3': floatReg('((dest * 4) + 3)'),
316 'AA64FpDest2P0': floatReg('((dest2 * 4) + 0)'),
317 'AA64FpDest2P1': floatReg('((dest2 * 4) + 1)'),
318 'AA64FpDest2P2': floatReg('((dest2 * 4) + 2)'),
319 'AA64FpDest2P3': floatReg('((dest2 * 4) + 3)'),
312 # Name ::= 'AA64Vec' OpSpec [LaneSpec]
313 # OpSpec ::= IOSpec [Index] [Plus]
314 # IOSpec ::= 'S' | 'D'
315 # Index ::= '0' | ... | '9'
316 # Plus ::= [PlusAmount] ['l']
317 # PlusAmount ::= 'p' [PlusAmount]
318 # LaneSpec ::= 'L' Index
319 #
320 # All the constituents are hierarchically defined as part of the Vector
321 # Register they belong to
320
322
321 'AA64FpOp1P0V0': floatReg('((((op1+0)) * 4) + 0)'),
322 'AA64FpOp1P1V0': floatReg('((((op1+0)) * 4) + 1)'),
323 'AA64FpOp1P2V0': floatReg('((((op1+0)) * 4) + 2)'),
324 'AA64FpOp1P3V0': floatReg('((((op1+0)) * 4) + 3)'),
323 'AA64FpOp1': vectorReg('op1',
324 {
325 'AA64FpOp1P0': vectorRegElem('0'),
326 'AA64FpOp1P1': vectorRegElem('1'),
327 'AA64FpOp1P2': vectorRegElem('2'),
328 'AA64FpOp1P3': vectorRegElem('3'),
329 'AA64FpOp1S': vectorRegElem('0', 'sf', zeroing = True),
330 'AA64FpOp1D': vectorRegElem('0', 'df', zeroing = True),
331 'AA64FpOp1Q': vectorRegElem('0', 'tud', zeroing = True)
332 }),
325
333
326 'AA64FpOp1P0V1': floatReg('((((op1+1)) * 4) + 0)'),
327 'AA64FpOp1P1V1': floatReg('((((op1+1)) * 4) + 1)'),
328 'AA64FpOp1P2V1': floatReg('((((op1+1)) * 4) + 2)'),
329 'AA64FpOp1P3V1': floatReg('((((op1+1)) * 4) + 3)'),
334 'AA64FpOp2': vectorReg('op2',
335 {
336 'AA64FpOp2P0': vectorRegElem('0'),
337 'AA64FpOp2P1': vectorRegElem('1'),
338 'AA64FpOp2P2': vectorRegElem('2'),
339 'AA64FpOp2P3': vectorRegElem('3'),
340 'AA64FpOp2S': vectorRegElem('0', 'sf', zeroing = True),
341 'AA64FpOp2D': vectorRegElem('0', 'df', zeroing = True),
342 'AA64FpOp2Q': vectorRegElem('0', 'tud', zeroing = True)
343 }),
330
344
331 'AA64FpOp1P0V2': floatReg('((((op1+2)) * 4) + 0)'),
332 'AA64FpOp1P1V2': floatReg('((((op1+2)) * 4) + 1)'),
333 'AA64FpOp1P2V2': floatReg('((((op1+2)) * 4) + 2)'),
334 'AA64FpOp1P3V2': floatReg('((((op1+2)) * 4) + 3)'),
345 'AA64FpOp3': vectorReg('op3',
346 {
347 'AA64FpOp3P0': vectorRegElem('0'),
348 'AA64FpOp3P1': vectorRegElem('1'),
349 'AA64FpOp3P2': vectorRegElem('2'),
350 'AA64FpOp3P3': vectorRegElem('3'),
351 'AA64FpOp3S': vectorRegElem('0', 'sf', zeroing = True),
352 'AA64FpOp3D': vectorRegElem('0', 'df', zeroing = True),
353 'AA64FpOp3Q': vectorRegElem('0', 'tud', zeroing = True)
354 }),
335
355
336 'AA64FpOp1P0V3': floatReg('((((op1+3)) * 4) + 0)'),
337 'AA64FpOp1P1V3': floatReg('((((op1+3)) * 4) + 1)'),
338 'AA64FpOp1P2V3': floatReg('((((op1+3)) * 4) + 2)'),
339 'AA64FpOp1P3V3': floatReg('((((op1+3)) * 4) + 3)'),
356 'AA64FpDest': vectorReg('dest',
357 {
358 'AA64FpDestP0': vectorRegElem('0'),
359 'AA64FpDestP1': vectorRegElem('1'),
360 'AA64FpDestP2': vectorRegElem('2'),
361 'AA64FpDestP3': vectorRegElem('3'),
362 'AA64FpDestS': vectorRegElem('0', 'sf', zeroing = True),
363 'AA64FpDestD': vectorRegElem('0', 'df', zeroing = True),
364 'AA64FpDestQ': vectorRegElem('0', 'tud', zeroing = True)
365 }),
340
366
341 'AA64FpOp1P0V0S': floatReg('((((op1+0)%32) * 4) + 0)'),
342 'AA64FpOp1P1V0S': floatReg('((((op1+0)%32) * 4) + 1)'),
343 'AA64FpOp1P2V0S': floatReg('((((op1+0)%32) * 4) + 2)'),
344 'AA64FpOp1P3V0S': floatReg('((((op1+0)%32) * 4) + 3)'),
367 'AA64FpDest2': vectorReg('dest2',
368 {
369 'AA64FpDest2P0': vectorRegElem('0'),
370 'AA64FpDest2P1': vectorRegElem('1'),
371 'AA64FpDest2P2': vectorRegElem('2'),
372 'AA64FpDest2P3': vectorRegElem('3'),
373 'AA64FpDest2S': vectorRegElem('0', 'sf', zeroing = True),
374 'AA64FpDest2D': vectorRegElem('0', 'df', zeroing = True),
375 'AA64FpDest2Q': vectorRegElem('0', 'tud', zeroing = True)
376 }),
345
377
346 'AA64FpOp1P0V1S': floatReg('((((op1+1)%32) * 4) + 0)'),
347 'AA64FpOp1P1V1S': floatReg('((((op1+1)%32) * 4) + 1)'),
348 'AA64FpOp1P2V1S': floatReg('((((op1+1)%32) * 4) + 2)'),
349 'AA64FpOp1P3V1S': floatReg('((((op1+1)%32) * 4) + 3)'),
378 'AA64FpOp1V0': vectorReg('op1',
379 {
380 'AA64FpOp1P0V0': vectorRegElem('0'),
381 'AA64FpOp1P1V0': vectorRegElem('1'),
382 'AA64FpOp1P2V0': vectorRegElem('2'),
383 'AA64FpOp1P3V0': vectorRegElem('3'),
384 'AA64FpOp1SV0': vectorRegElem('0', 'sf', zeroing = True),
385 'AA64FpOp1DV0': vectorRegElem('0', 'df', zeroing = True),
386 'AA64FpOp1QV0': vectorRegElem('0', 'tud', zeroing = True)
387 }),
350
388
351 'AA64FpOp1P0V2S': floatReg('((((op1+2)%32) * 4) + 0)'),
352 'AA64FpOp1P1V2S': floatReg('((((op1+2)%32) * 4) + 1)'),
353 'AA64FpOp1P2V2S': floatReg('((((op1+2)%32) * 4) + 2)'),
354 'AA64FpOp1P3V2S': floatReg('((((op1+2)%32) * 4) + 3)'),
389 'AA64FpOp1V1': vectorReg('op1+1',
390 {
391 'AA64FpOp1P0V1': vectorRegElem('0'),
392 'AA64FpOp1P1V1': vectorRegElem('1'),
393 'AA64FpOp1P2V1': vectorRegElem('2'),
394 'AA64FpOp1P3V1': vectorRegElem('3'),
395 'AA64FpOp1SV1': vectorRegElem('0', 'sf', zeroing = True),
396 'AA64FpOp1DV1': vectorRegElem('0', 'df', zeroing = True),
397 'AA64FpOp1QV1': vectorRegElem('0', 'tud', zeroing = True)
398 }),
355
399
356 'AA64FpOp1P0V3S': floatReg('((((op1+3)%32) * 4) + 0)'),
357 'AA64FpOp1P1V3S': floatReg('((((op1+3)%32) * 4) + 1)'),
358 'AA64FpOp1P2V3S': floatReg('((((op1+3)%32) * 4) + 2)'),
359 'AA64FpOp1P3V3S': floatReg('((((op1+3)%32) * 4) + 3)'),
400 'AA64FpOp1V2': vectorReg('op1+2',
401 {
402 'AA64FpOp1P0V2': vectorRegElem('0'),
403 'AA64FpOp1P1V2': vectorRegElem('1'),
404 'AA64FpOp1P2V2': vectorRegElem('2'),
405 'AA64FpOp1P3V2': vectorRegElem('3'),
406 'AA64FpOp1SV2': vectorRegElem('0', 'sf', zeroing = True),
407 'AA64FpOp1DV2': vectorRegElem('0', 'df', zeroing = True),
408 'AA64FpOp1QV2': vectorRegElem('0', 'tud', zeroing = True)
409 }),
360
410
361 'AA64FpDestP0V0': floatReg('((((dest+0)) * 4) + 0)'),
362 'AA64FpDestP1V0': floatReg('((((dest+0)) * 4) + 1)'),
363 'AA64FpDestP2V0': floatReg('((((dest+0)) * 4) + 2)'),
364 'AA64FpDestP3V0': floatReg('((((dest+0)) * 4) + 3)'),
411 'AA64FpOp1V3': vectorReg('op1+3',
412 {
413 'AA64FpOp1P0V3': vectorRegElem('0'),
414 'AA64FpOp1P1V3': vectorRegElem('1'),
415 'AA64FpOp1P2V3': vectorRegElem('2'),
416 'AA64FpOp1P3V3': vectorRegElem('3'),
417 'AA64FpOp1SV3': vectorRegElem('0', 'sf', zeroing = True),
418 'AA64FpOp1DV3': vectorRegElem('0', 'df', zeroing = True),
419 'AA64FpOp1QV3': vectorRegElem('0', 'tud', zeroing = True)
420 }),
365
421
366 'AA64FpDestP0V1': floatReg('((((dest+1)) * 4) + 0)'),
367 'AA64FpDestP1V1': floatReg('((((dest+1)) * 4) + 1)'),
368 'AA64FpDestP2V1': floatReg('((((dest+1)) * 4) + 2)'),
369 'AA64FpDestP3V1': floatReg('((((dest+1)) * 4) + 3)'),
422 'AA64FpOp1V0S': vectorReg('(op1+0)%32',
423 {
424 'AA64FpOp1P0V0S': vectorRegElem('0'),
425 'AA64FpOp1P1V0S': vectorRegElem('1'),
426 'AA64FpOp1P2V0S': vectorRegElem('2'),
427 'AA64FpOp1P3V0S': vectorRegElem('3'),
428 'AA64FpOp1SV0S': vectorRegElem('0', 'sf', zeroing = True),
429 'AA64FpOp1DV0S': vectorRegElem('0', 'df', zeroing = True),
430 'AA64FpOp1QV0S': vectorRegElem('0', 'tud', zeroing = True)
431 }),
370
432
371 'AA64FpDestP0V0L': floatReg('((((dest+0)%32) * 4) + 0)'),
372 'AA64FpDestP1V0L': floatReg('((((dest+0)%32) * 4) + 1)'),
373 'AA64FpDestP2V0L': floatReg('((((dest+0)%32) * 4) + 2)'),
374 'AA64FpDestP3V0L': floatReg('((((dest+0)%32) * 4) + 3)'),
433 'AA64FpOp1V1S': vectorReg('(op1+1)%32',
434 {
435 'AA64FpOp1P0V1S': vectorRegElem('0'),
436 'AA64FpOp1P1V1S': vectorRegElem('1'),
437 'AA64FpOp1P2V1S': vectorRegElem('2'),
438 'AA64FpOp1P3V1S': vectorRegElem('3'),
439 'AA64FpOp1SV1S': vectorRegElem('0', 'sf', zeroing = True),
440 'AA64FpOp1DV1S': vectorRegElem('0', 'df', zeroing = True),
441 'AA64FpOp1QV1S': vectorRegElem('0', 'tud', zeroing = True)
442 }),
375
443
376 'AA64FpDestP0V1L': floatReg('((((dest+1)%32) * 4) + 0)'),
377 'AA64FpDestP1V1L': floatReg('((((dest+1)%32) * 4) + 1)'),
378 'AA64FpDestP2V1L': floatReg('((((dest+1)%32) * 4) + 2)'),
379 'AA64FpDestP3V1L': floatReg('((((dest+1)%32) * 4) + 3)'),
444 'AA64FpOp1V2S': vectorReg('(op1+2)%32',
445 {
446 'AA64FpOp1P0V2S': vectorRegElem('0'),
447 'AA64FpOp1P1V2S': vectorRegElem('1'),
448 'AA64FpOp1P2V2S': vectorRegElem('2'),
449 'AA64FpOp1P3V2S': vectorRegElem('3'),
450 'AA64FpOp1SV2S': vectorRegElem('0', 'sf', zeroing = True),
451 'AA64FpOp1DV2S': vectorRegElem('0', 'df', zeroing = True),
452 'AA64FpOp1QV2S': vectorRegElem('0', 'tud', zeroing = True)
453 }),
380
454
455 'AA64FpOp1V3S': vectorReg('(op1+3)%32',
456 {
457 'AA64FpOp1P0V3S': vectorRegElem('0'),
458 'AA64FpOp1P1V3S': vectorRegElem('1'),
459 'AA64FpOp1P2V3S': vectorRegElem('2'),
460 'AA64FpOp1P3V3S': vectorRegElem('3'),
461 'AA64FpOp1SV3S': vectorRegElem('0', 'sf', zeroing = True),
462 'AA64FpOp1DV3S': vectorRegElem('0', 'df', zeroing = True),
463 'AA64FpOp1QV3S': vectorRegElem('0', 'tud', zeroing = True)
464 }),
465
466 'AA64FpDestV0': vectorReg('(dest+0)',
467 {
468 'AA64FpDestP0V0': vectorRegElem('0'),
469 'AA64FpDestP1V0': vectorRegElem('1'),
470 'AA64FpDestP2V0': vectorRegElem('2'),
471 'AA64FpDestP3V0': vectorRegElem('3'),
472 'AA64FpDestSV0': vectorRegElem('0', 'sf', zeroing = True),
473 'AA64FpDestDV0': vectorRegElem('0', 'df', zeroing = True),
474 'AA64FpDestQV0': vectorRegElem('0', 'tud', zeroing = True)
475 }),
476
477 'AA64FpDestV1': vectorReg('(dest+1)',
478 {
479 'AA64FpDestP0V1': vectorRegElem('0'),
480 'AA64FpDestP1V1': vectorRegElem('1'),
481 'AA64FpDestP2V1': vectorRegElem('2'),
482 'AA64FpDestP3V1': vectorRegElem('3'),
483 'AA64FpDestSV1': vectorRegElem('0', 'sf', zeroing = True),
484 'AA64FpDestDV1': vectorRegElem('0', 'df', zeroing = True),
485 'AA64FpDestQV1': vectorRegElem('0', 'tud', zeroing = True)
486 }),
487
488 'AA64FpDestV0L': vectorReg('(dest+0)%32',
489 {
490 'AA64FpDestP0V0L': vectorRegElem('0'),
491 'AA64FpDestP1V0L': vectorRegElem('1'),
492 'AA64FpDestP2V0L': vectorRegElem('2'),
493 'AA64FpDestP3V0L': vectorRegElem('3'),
494 'AA64FpDestSV0L': vectorRegElem('0', 'sf', zeroing = True),
495 'AA64FpDestDV0L': vectorRegElem('0', 'df', zeroing = True),
496 'AA64FpDestQV0L': vectorRegElem('0', 'tud', zeroing = True)
497 }),
498
499 'AA64FpDestV1L': vectorReg('(dest+1)%32',
500 {
501 'AA64FpDestP0V1L': vectorRegElem('0'),
502 'AA64FpDestP1V1L': vectorRegElem('1'),
503 'AA64FpDestP2V1L': vectorRegElem('2'),
504 'AA64FpDestP3V1L': vectorRegElem('3'),
505 'AA64FpDestSV1L': vectorRegElem('0', 'sf', zeroing = True),
506 'AA64FpDestDV1L': vectorRegElem('0', 'df', zeroing = True),
507 'AA64FpDestQV1L': vectorRegElem('0', 'tud', zeroing = True)
508 }),
509
381 #Abstracted control reg operands
382 'MiscDest': cntrlReg('dest'),
383 'MiscOp1': cntrlReg('op1'),
384 'MiscNsBankedDest': cntrlNsBankedReg('dest'),
385 'MiscNsBankedOp1': cntrlNsBankedReg('op1'),
386 'MiscNsBankedDest64': cntrlNsBankedReg64('dest'),
387 'MiscNsBankedOp164': cntrlNsBankedReg64('op1'),
388

--- 65 unchanged lines hidden --- 		510 #Abstracted control reg operands
511 'MiscDest': cntrlReg('dest'),
512 'MiscOp1': cntrlReg('op1'),
513 'MiscNsBankedDest': cntrlNsBankedReg('dest'),
514 'MiscNsBankedOp1': cntrlNsBankedReg('op1'),
515 'MiscNsBankedDest64': cntrlNsBankedReg64('dest'),
516 'MiscNsBankedOp164': cntrlNsBankedReg64('op1'),
517

--- 65 unchanged lines hidden ---