operands.isa (10037:5cac77888310) operands.isa (10338:8bee5f4edb92)
1// -*- mode:c++ -*-
1// -*- mode:c++ -*-
2// Copyright (c) 2010-2013 ARM Limited
2// Copyright (c) 2010-2014 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated

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146 def intRegIWPC(idx):
147 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
148 maybePCRead, maybeIWPCWrite)
149
150 def intRegAIWPC(idx):
151 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
152 maybePCRead, maybeAIWPCWrite)
153
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated

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146 def intRegIWPC(idx):
147 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
148 maybePCRead, maybeIWPCWrite)
149
150 def intRegAIWPC(idx):
151 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
152 maybePCRead, maybeAIWPCWrite)
153
154 def intRegCC(idx):
155 return ('IntReg', 'uw', idx, None, srtNormal)
154 def ccReg(idx):
155 return ('CCReg', 'uw', idx, None, srtNormal)
156
157 def cntrlReg(idx, id = srtNormal, type = 'uw'):
158 return ('ControlReg', type, idx, None, id)
159
160 def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'):
161 return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
162
163 def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'):

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216 'R1': intRegNPC('1'),
217 'R2': intRegNPC('2'),
218 'R3': intRegNPC('3'),
219 'X0': intRegX64('0'),
220 'X1': intRegX64('1'),
221 'X2': intRegX64('2'),
222 'X3': intRegX64('3'),
223
156
157 def cntrlReg(idx, id = srtNormal, type = 'uw'):
158 return ('ControlReg', type, idx, None, id)
159
160 def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'):
161 return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
162
163 def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'):

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216 'R1': intRegNPC('1'),
217 'R2': intRegNPC('2'),
218 'R3': intRegNPC('3'),
219 'X0': intRegX64('0'),
220 'X1': intRegX64('1'),
221 'X2': intRegX64('2'),
222 'X3': intRegX64('3'),
223
224 #Pseudo integer condition code registers
225 'CondCodesNZ': intRegCC('INTREG_CONDCODES_NZ'),
226 'CondCodesC': intRegCC('INTREG_CONDCODES_C'),
227 'CondCodesV': intRegCC('INTREG_CONDCODES_V'),
228 'CondCodesGE': intRegCC('INTREG_CONDCODES_GE'),
229 'OptCondCodesNZ': intRegCC(
230 '''(condCode == COND_AL || condCode == COND_UC ||
231 condCode == COND_CC || condCode == COND_CS ||
232 condCode == COND_VS || condCode == COND_VC) ?
233 INTREG_ZERO : INTREG_CONDCODES_NZ'''),
234 'OptCondCodesC': intRegCC(
235 '''(condCode == COND_HI || condCode == COND_LS ||
224 # Condition code registers
225 'CondCodesNZ': ccReg('CCREG_NZ'),
226 'CondCodesC': ccReg('CCREG_C'),
227 'CondCodesV': ccReg('CCREG_V'),
228 'CondCodesGE': ccReg('CCREG_GE'),
229 'OptCondCodesNZ': ccReg(
230 '''((condCode == COND_AL || condCode == COND_UC ||
231 condCode == COND_CC || condCode == COND_CS ||
232 condCode == COND_VS || condCode == COND_VC) ?
233 CCREG_ZERO : CCREG_NZ)'''),
234 'OptCondCodesC': ccReg(
235 '''((condCode == COND_HI || condCode == COND_LS ||
236 condCode == COND_CS || condCode == COND_CC) ?
236 condCode == COND_CS || condCode == COND_CC) ?
237 INTREG_CONDCODES_C : INTREG_ZERO'''),
238 'OptShiftRmCondCodesC': intRegCC(
239 '''(condCode == COND_HI || condCode == COND_LS ||
240 condCode == COND_CS || condCode == COND_CC ||
241 shiftType == ROR) ?
242 INTREG_CONDCODES_C : INTREG_ZERO'''),
243 'OptCondCodesV': intRegCC(
244 '''(condCode == COND_VS || condCode == COND_VC ||
245 condCode == COND_GE || condCode == COND_LT ||
246 condCode == COND_GT || condCode == COND_LE) ?
247 INTREG_CONDCODES_V : INTREG_ZERO'''),
248 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'),
237 CCREG_C : CCREG_ZERO)'''),
238 'OptShiftRmCondCodesC': ccReg(
239 '''((condCode == COND_HI || condCode == COND_LS ||
240 condCode == COND_CS || condCode == COND_CC ||
241 shiftType == ROR) ?
242 CCREG_C : CCREG_ZERO)'''),
243 'OptCondCodesV': ccReg(
244 '''((condCode == COND_VS || condCode == COND_VC ||
245 condCode == COND_GE || condCode == COND_LT ||
246 condCode == COND_GT || condCode == COND_LE) ?
247 CCREG_V : CCREG_ZERO)'''),
248 'FpCondCodes': ccReg('CCREG_FP'),
249
250 #Abstracted floating point reg operands
251 'FpDest': floatReg('(dest + 0)'),
252 'FpDestP0': floatReg('(dest + 0)'),
253 'FpDestP1': floatReg('(dest + 1)'),
254 'FpDestP2': floatReg('(dest + 2)'),
255 'FpDestP3': floatReg('(dest + 3)'),
256 'FpDestP4': floatReg('(dest + 4)'),

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250 #Abstracted floating point reg operands
251 'FpDest': floatReg('(dest + 0)'),
252 'FpDestP0': floatReg('(dest + 0)'),
253 'FpDestP1': floatReg('(dest + 1)'),
254 'FpDestP2': floatReg('(dest + 2)'),
255 'FpDestP3': floatReg('(dest + 3)'),
256 'FpDestP4': floatReg('(dest + 4)'),

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