1// -*- mode:c++ -*- 2// Copyright (c) 2010 ARM Limited 3// All rights reserved 4// 5// The license below extends only to copyright in the software and shall 6// not be construed as granting a license to any other intellectual 7// property including but not limited to intellectual property relating 8// to a hardware implementation of the functionality of the software --- 66 unchanged lines hidden (view full) --- 75 setNextPC(xc, %(final_val)s); 76 } else { 77 setIWNextPC(xc, %(final_val)s); 78 } 79 } else { 80 xc->%(func)s(this, %(op_idx)s, %(final_val)s); 81 } 82 ''' |
83 84 #PCState operands need to have a sorting index (the number at the end) 85 #less than all the integer registers which might update the PC. That way 86 #if the flag bits of the pc state are updated and a branch happens through 87 #R15, the updates are layered properly and the R15 update isn't lost. 88 srtNormal = 5 89 srtCpsr = 4 90 srtBase = 3 91 srtPC = 2 92 srtMode = 1 93 srtEPC = 0 94 95 def floatReg(idx): 96 return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal) 97 98 def intReg(idx): 99 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal, 100 maybePCRead, maybePCWrite) 101 102 def intRegNPC(idx): 103 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal) 104 105 def intRegAPC(idx, id = srtNormal): 106 return ('IntReg', 'uw', idx, 'IsInteger', id, 107 maybeAlignedPCRead, maybePCWrite) 108 109 def intRegIWPC(idx): 110 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal, 111 maybePCRead, maybeIWPCWrite) 112 113 def intRegAIWPC(idx): 114 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal, 115 maybePCRead, maybeAIWPCWrite) 116 117 def intRegCC(idx): 118 return ('IntReg', 'uw', idx, None, srtNormal) 119 120 def cntrlReg(idx, id = srtNormal, type = 'uw'): 121 return ('ControlReg', type, idx, (None, None, 'IsControl'), id) 122 123 def cntrlRegNC(idx, id = srtNormal, type = 'uw'): 124 return ('ControlReg', type, idx, None, id) 125 126 def pcStateReg(idx, id): 127 return ('PCState', 'uw', idx, (None, None, 'IsControl'), id) |
128}}; 129 130def operands {{ 131 #Abstracted integer reg operands |
132 'Dest': intReg('dest'), 133 'IWDest': intRegIWPC('dest'), 134 'AIWDest': intRegAIWPC('dest'), 135 'Dest2': intReg('dest2'), 136 'Result': intReg('result'), 137 'Base': intRegAPC('base', id = srtBase), 138 'Index': intReg('index'), 139 'Shift': intReg('shift'), 140 'Op1': intReg('op1'), 141 'Op2': intReg('op2'), 142 'Op3': intReg('op3'), 143 'Reg0': intReg('reg0'), 144 'Reg1': intReg('reg1'), 145 'Reg2': intReg('reg2'), 146 'Reg3': intReg('reg3'), |
147 |
148 #Fixed index integer reg operands 149 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'), 150 'LR': intRegNPC('INTREG_LR'), 151 'R7': intRegNPC('7'), 152 'R0': intRegNPC('0'), 153 'R1': intRegNPC('0'), 154 'R2': intRegNPC('1'), 155 156 #Pseudo integer condition code registers 157 'CondCodes': intRegCC('INTREG_CONDCODES'), 158 'OptCondCodes': intRegCC( |
159 '''(condCode == COND_AL || condCode == COND_UC) ? |
160 INTREG_ZERO : INTREG_CONDCODES'''), 161 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'), |
162 |
163 #Abstracted floating point reg operands 164 'FpDest': floatReg('(dest + 0)'), 165 'FpDestP0': floatReg('(dest + 0)'), 166 'FpDestP1': floatReg('(dest + 1)'), 167 'FpDestP2': floatReg('(dest + 2)'), 168 'FpDestP3': floatReg('(dest + 3)'), 169 'FpDestP4': floatReg('(dest + 4)'), 170 'FpDestP5': floatReg('(dest + 5)'), 171 'FpDestP6': floatReg('(dest + 6)'), 172 'FpDestP7': floatReg('(dest + 7)'), 173 'FpDestS0P0': floatReg('(dest + step * 0 + 0)'), 174 'FpDestS0P1': floatReg('(dest + step * 0 + 1)'), 175 'FpDestS1P0': floatReg('(dest + step * 1 + 0)'), 176 'FpDestS1P1': floatReg('(dest + step * 1 + 1)'), 177 'FpDestS2P0': floatReg('(dest + step * 2 + 0)'), 178 'FpDestS2P1': floatReg('(dest + step * 2 + 1)'), 179 'FpDestS3P0': floatReg('(dest + step * 3 + 0)'), 180 'FpDestS3P1': floatReg('(dest + step * 3 + 1)'), 181 182 'FpDest2': floatReg('(dest2 + 0)'), 183 'FpDest2P0': floatReg('(dest2 + 0)'), 184 'FpDest2P1': floatReg('(dest2 + 1)'), 185 'FpDest2P2': floatReg('(dest2 + 2)'), 186 'FpDest2P3': floatReg('(dest2 + 3)'), 187 188 'FpOp1': floatReg('(op1 + 0)'), 189 'FpOp1P0': floatReg('(op1 + 0)'), 190 'FpOp1P1': floatReg('(op1 + 1)'), 191 'FpOp1P2': floatReg('(op1 + 2)'), 192 'FpOp1P3': floatReg('(op1 + 3)'), 193 'FpOp1P4': floatReg('(op1 + 4)'), 194 'FpOp1P5': floatReg('(op1 + 5)'), 195 'FpOp1P6': floatReg('(op1 + 6)'), 196 'FpOp1P7': floatReg('(op1 + 7)'), 197 'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'), 198 'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'), 199 'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'), 200 'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'), 201 'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'), 202 'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'), 203 'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'), 204 'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'), 205 206 'FpOp2': floatReg('(op2 + 0)'), 207 'FpOp2P0': floatReg('(op2 + 0)'), 208 'FpOp2P1': floatReg('(op2 + 1)'), 209 'FpOp2P2': floatReg('(op2 + 2)'), 210 'FpOp2P3': floatReg('(op2 + 3)'), 211 212 #Abstracted control reg operands 213 'MiscDest': cntrlReg('dest'), 214 'MiscOp1': cntrlReg('op1'), 215 216 #Fixed index control regs 217 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr), 218 'Itstate': cntrlRegNC('MISCREG_ITSTATE', type = 'ub'), 219 'Spsr': cntrlRegNC('MISCREG_SPSR'), 220 'Fpsr': cntrlRegNC('MISCREG_FPSR'), 221 'Fpsid': cntrlRegNC('MISCREG_FPSID'), 222 'Fpscr': cntrlRegNC('MISCREG_FPSCR'), 223 'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'), 224 'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'), 225 'Cpacr': cntrlReg('MISCREG_CPACR'), 226 'Fpexc': cntrlRegNC('MISCREG_FPEXC'), 227 'Sctlr': cntrlRegNC('MISCREG_SCTLR'), 228 'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'), 229 |
230 #Register fields for microops |
231 'Ra' : intReg('ura'), 232 'IWRa' : intRegIWPC('ura'), 233 'Fa' : floatReg('ura'), 234 'Rb' : intReg('urb'), 235 'Rc' : intReg('urc'), |
236 237 #Memory Operand |
238 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal), |
239 |
240 #PCState fields 241 'PC': pcStateReg('instPC', srtPC), 242 'NPC': pcStateReg('instNPC', srtPC), 243 'pNPC': pcStateReg('instNPC', srtEPC), 244 'IWNPC': pcStateReg('instIWNPC', srtPC), 245 'Thumb': pcStateReg('thumb', srtPC), 246 'NextThumb': pcStateReg('nextThumb', srtMode), 247 'NextJazelle': pcStateReg('nextJazelle', srtMode), 248 249 #Register operands depending on a field in the instruction encoding. These 250 #should be avoided since they may not be portable across different 251 #encodings of the same instruction. 252 'Rd': intReg('RD'), 253 'Rm': intReg('RM'), 254 'Rs': intReg('RS'), 255 'Rn': intReg('RN'), 256 'Rt': intReg('RT') |
257}}; |