57,58c57
< ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
< xc->%(func)s(this, %(op_idx)s))
---
> ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
61c60
< ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) :
---
> ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
84,88d82
<
< readNPC = 'xc->readNextPC() & ~PcModeMask'
< writeNPC = 'setNextPC(xc, %(final_val)s)'
< writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
< forceNPC = 'xc->setNextPC(%(final_val)s)'
93c87
< 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
---
> 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
95,112c89,106
< 'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
< 'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
< 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2),
< 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2),
< 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2),
< 'FpDestP4': ('FloatReg', 'sf', '(dest + 4)', 'IsFloating', 2),
< 'FpDestP5': ('FloatReg', 'sf', '(dest + 5)', 'IsFloating', 2),
< 'FpDestP6': ('FloatReg', 'sf', '(dest + 6)', 'IsFloating', 2),
< 'FpDestP7': ('FloatReg', 'sf', '(dest + 7)', 'IsFloating', 2),
< 'FpDestS0P0': ('FloatReg', 'sf', '(dest + step * 0 + 0)', 'IsFloating', 2),
< 'FpDestS0P1': ('FloatReg', 'sf', '(dest + step * 0 + 1)', 'IsFloating', 2),
< 'FpDestS1P0': ('FloatReg', 'sf', '(dest + step * 1 + 0)', 'IsFloating', 2),
< 'FpDestS1P1': ('FloatReg', 'sf', '(dest + step * 1 + 1)', 'IsFloating', 2),
< 'FpDestS2P0': ('FloatReg', 'sf', '(dest + step * 2 + 0)', 'IsFloating', 2),
< 'FpDestS2P1': ('FloatReg', 'sf', '(dest + step * 2 + 1)', 'IsFloating', 2),
< 'FpDestS3P0': ('FloatReg', 'sf', '(dest + step * 3 + 0)', 'IsFloating', 2),
< 'FpDestS3P1': ('FloatReg', 'sf', '(dest + step * 3 + 1)', 'IsFloating', 2),
< 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
---
> 'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3),
> 'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3),
> 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 3),
> 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 3),
> 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 3),
> 'FpDestP4': ('FloatReg', 'sf', '(dest + 4)', 'IsFloating', 3),
> 'FpDestP5': ('FloatReg', 'sf', '(dest + 5)', 'IsFloating', 3),
> 'FpDestP6': ('FloatReg', 'sf', '(dest + 6)', 'IsFloating', 3),
> 'FpDestP7': ('FloatReg', 'sf', '(dest + 7)', 'IsFloating', 3),
> 'FpDestS0P0': ('FloatReg', 'sf', '(dest + step * 0 + 0)', 'IsFloating', 3),
> 'FpDestS0P1': ('FloatReg', 'sf', '(dest + step * 0 + 1)', 'IsFloating', 3),
> 'FpDestS1P0': ('FloatReg', 'sf', '(dest + step * 1 + 0)', 'IsFloating', 3),
> 'FpDestS1P1': ('FloatReg', 'sf', '(dest + step * 1 + 1)', 'IsFloating', 3),
> 'FpDestS2P0': ('FloatReg', 'sf', '(dest + step * 2 + 0)', 'IsFloating', 3),
> 'FpDestS2P1': ('FloatReg', 'sf', '(dest + step * 2 + 1)', 'IsFloating', 3),
> 'FpDestS3P0': ('FloatReg', 'sf', '(dest + step * 3 + 0)', 'IsFloating', 3),
> 'FpDestS3P1': ('FloatReg', 'sf', '(dest + step * 3 + 1)', 'IsFloating', 3),
> 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 3,
114c108
< 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
---
> 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 3,
116,121c110,115
< 'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
< 'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
< 'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2),
< 'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2),
< 'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 2),
< 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
---
> 'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3),
> 'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3),
> 'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 3),
> 'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 3),
> 'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 3),
> 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
123c117
< 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
---
> 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
127,129c121,123
< 'IsInteger', 2),
< 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
< 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,
---
> 'IsInteger', 3),
> 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 3),
> 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
131c125
< 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
---
> 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 3,
133c127
< 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
---
> 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
135,153c129,147
< 'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
< 'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
< 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2),
< 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2),
< 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2),
< 'FpOp1P4': ('FloatReg', 'sf', '(op1 + 4)', 'IsFloating', 2),
< 'FpOp1P5': ('FloatReg', 'sf', '(op1 + 5)', 'IsFloating', 2),
< 'FpOp1P6': ('FloatReg', 'sf', '(op1 + 6)', 'IsFloating', 2),
< 'FpOp1P7': ('FloatReg', 'sf', '(op1 + 7)', 'IsFloating', 2),
< 'FpOp1S0P0': ('FloatReg', 'sf', '(op1 + step * 0 + 0)', 'IsFloating', 2),
< 'FpOp1S0P1': ('FloatReg', 'sf', '(op1 + step * 0 + 1)', 'IsFloating', 2),
< 'FpOp1S1P0': ('FloatReg', 'sf', '(op1 + step * 1 + 0)', 'IsFloating', 2),
< 'FpOp1S1P1': ('FloatReg', 'sf', '(op1 + step * 1 + 1)', 'IsFloating', 2),
< 'FpOp1S2P0': ('FloatReg', 'sf', '(op1 + step * 2 + 0)', 'IsFloating', 2),
< 'FpOp1S2P1': ('FloatReg', 'sf', '(op1 + step * 2 + 1)', 'IsFloating', 2),
< 'FpOp1S3P0': ('FloatReg', 'sf', '(op1 + step * 3 + 0)', 'IsFloating', 2),
< 'FpOp1S3P1': ('FloatReg', 'sf', '(op1 + step * 3 + 1)', 'IsFloating', 2),
< 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),
< 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2,
---
> 'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3),
> 'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3),
> 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 3),
> 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 3),
> 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 3),
> 'FpOp1P4': ('FloatReg', 'sf', '(op1 + 4)', 'IsFloating', 3),
> 'FpOp1P5': ('FloatReg', 'sf', '(op1 + 5)', 'IsFloating', 3),
> 'FpOp1P6': ('FloatReg', 'sf', '(op1 + 6)', 'IsFloating', 3),
> 'FpOp1P7': ('FloatReg', 'sf', '(op1 + 7)', 'IsFloating', 3),
> 'FpOp1S0P0': ('FloatReg', 'sf', '(op1 + step * 0 + 0)', 'IsFloating', 3),
> 'FpOp1S0P1': ('FloatReg', 'sf', '(op1 + step * 0 + 1)', 'IsFloating', 3),
> 'FpOp1S1P0': ('FloatReg', 'sf', '(op1 + step * 1 + 0)', 'IsFloating', 3),
> 'FpOp1S1P1': ('FloatReg', 'sf', '(op1 + step * 1 + 1)', 'IsFloating', 3),
> 'FpOp1S2P0': ('FloatReg', 'sf', '(op1 + step * 2 + 0)', 'IsFloating', 3),
> 'FpOp1S2P1': ('FloatReg', 'sf', '(op1 + step * 2 + 1)', 'IsFloating', 3),
> 'FpOp1S3P0': ('FloatReg', 'sf', '(op1 + step * 3 + 0)', 'IsFloating', 3),
> 'FpOp1S3P1': ('FloatReg', 'sf', '(op1 + step * 3 + 1)', 'IsFloating', 3),
> 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 3),
> 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 3,
155,160c149,154
< 'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
< 'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
< 'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2),
< 'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2),
< 'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2),
< 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2,
---
> 'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3),
> 'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3),
> 'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 3),
> 'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 3),
> 'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 3),
> 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 3,
162c156
< 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2,
---
> 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 3,
164c158
< 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2,
---
> 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 3,
166c160
< 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2,
---
> 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 3,
168c162
< 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 2,
---
> 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 3,
170c164
< 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 2,
---
> 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 3,
173,178c167,172
< 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 2, maybePCRead, maybePCWrite),
< 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
< 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite),
< 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite),
< 'R7': ('IntReg', 'uw', '7', 'IsInteger', 2),
< 'R0': ('IntReg', 'uw', '0', 'IsInteger', 2),
---
> 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 3, maybePCRead, maybePCWrite),
> 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 3, maybePCRead, maybePCWrite),
> 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
> 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 3, maybePCRead, maybePCWrite),
> 'R7': ('IntReg', 'uw', '7', 'IsInteger', 3),
> 'R0': ('IntReg', 'uw', '0', 'IsInteger', 3),
180,181c174,175
< 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2),
< 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2),
---
> 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 3),
> 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 3),
184,185c178,179
< INTREG_ZERO : INTREG_CONDCODES''', None, 2),
< 'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 2),
---
> INTREG_ZERO : INTREG_CONDCODES''', None, 3),
> 'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 3),
188,189c182,183
< 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite),
< 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2,
---
> 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 3, maybePCRead, maybePCWrite),
> 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 3,
191,193c185,187
< 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2),
< 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite),
< 'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 2, maybePCRead, maybePCWrite),
---
> 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 3),
> 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 3, maybePCRead, maybePCWrite),
> 'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 3, maybePCRead, maybePCWrite),
196,198c190,192
< 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2),
< 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
< 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2),
---
> 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 3),
> 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 3),
> 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3),
201c195
< 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2),
---
> 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 3),
203,219c197,211
< 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1),
< 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 2),
< 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2),
< 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2),
< 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2),
< 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
< 'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 2),
< 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
< 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2),
< 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2),
< 'PC': ('PC', 'ud', None, None, 2),
< 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
< readNPC, writeNPC),
< 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
< readNPC, forceNPC),
< 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
< readNPC, writeIWNPC),
---
> 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 2),
> 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 3),
> 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 3),
> 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 3),
> 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 3),
> 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 3),
> 'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 3),
> 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 3),
> 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 3),
> 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 3),
> #PCS needs to have a sorting index (the number at the end) less than all
> #the integer registers which might update the PC. That way if the flag
> #bits of the pc state are updated and a branch happens through R15, the
> #updates are layered properly and the R15 update isn't lost.
> 'PCS': ('PCState', 'uw', None, (None, None, 'IsControl'), 0)
< ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
< xc->%(func)s(this, %(op_idx)s))
---
> ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
61c60
< ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) :
---
> ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
84,88d82
<
< readNPC = 'xc->readNextPC() & ~PcModeMask'
< writeNPC = 'setNextPC(xc, %(final_val)s)'
< writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
< forceNPC = 'xc->setNextPC(%(final_val)s)'
93c87
< 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
---
> 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
95,112c89,106
< 'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
< 'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
< 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2),
< 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2),
< 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2),
< 'FpDestP4': ('FloatReg', 'sf', '(dest + 4)', 'IsFloating', 2),
< 'FpDestP5': ('FloatReg', 'sf', '(dest + 5)', 'IsFloating', 2),
< 'FpDestP6': ('FloatReg', 'sf', '(dest + 6)', 'IsFloating', 2),
< 'FpDestP7': ('FloatReg', 'sf', '(dest + 7)', 'IsFloating', 2),
< 'FpDestS0P0': ('FloatReg', 'sf', '(dest + step * 0 + 0)', 'IsFloating', 2),
< 'FpDestS0P1': ('FloatReg', 'sf', '(dest + step * 0 + 1)', 'IsFloating', 2),
< 'FpDestS1P0': ('FloatReg', 'sf', '(dest + step * 1 + 0)', 'IsFloating', 2),
< 'FpDestS1P1': ('FloatReg', 'sf', '(dest + step * 1 + 1)', 'IsFloating', 2),
< 'FpDestS2P0': ('FloatReg', 'sf', '(dest + step * 2 + 0)', 'IsFloating', 2),
< 'FpDestS2P1': ('FloatReg', 'sf', '(dest + step * 2 + 1)', 'IsFloating', 2),
< 'FpDestS3P0': ('FloatReg', 'sf', '(dest + step * 3 + 0)', 'IsFloating', 2),
< 'FpDestS3P1': ('FloatReg', 'sf', '(dest + step * 3 + 1)', 'IsFloating', 2),
< 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
---
> 'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3),
> 'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 3),
> 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 3),
> 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 3),
> 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 3),
> 'FpDestP4': ('FloatReg', 'sf', '(dest + 4)', 'IsFloating', 3),
> 'FpDestP5': ('FloatReg', 'sf', '(dest + 5)', 'IsFloating', 3),
> 'FpDestP6': ('FloatReg', 'sf', '(dest + 6)', 'IsFloating', 3),
> 'FpDestP7': ('FloatReg', 'sf', '(dest + 7)', 'IsFloating', 3),
> 'FpDestS0P0': ('FloatReg', 'sf', '(dest + step * 0 + 0)', 'IsFloating', 3),
> 'FpDestS0P1': ('FloatReg', 'sf', '(dest + step * 0 + 1)', 'IsFloating', 3),
> 'FpDestS1P0': ('FloatReg', 'sf', '(dest + step * 1 + 0)', 'IsFloating', 3),
> 'FpDestS1P1': ('FloatReg', 'sf', '(dest + step * 1 + 1)', 'IsFloating', 3),
> 'FpDestS2P0': ('FloatReg', 'sf', '(dest + step * 2 + 0)', 'IsFloating', 3),
> 'FpDestS2P1': ('FloatReg', 'sf', '(dest + step * 2 + 1)', 'IsFloating', 3),
> 'FpDestS3P0': ('FloatReg', 'sf', '(dest + step * 3 + 0)', 'IsFloating', 3),
> 'FpDestS3P1': ('FloatReg', 'sf', '(dest + step * 3 + 1)', 'IsFloating', 3),
> 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 3,
114c108
< 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
---
> 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 3,
116,121c110,115
< 'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
< 'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
< 'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2),
< 'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2),
< 'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 2),
< 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
---
> 'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3),
> 'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 3),
> 'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 3),
> 'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 3),
> 'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 3),
> 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
123c117
< 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
---
> 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 3,
127,129c121,123
< 'IsInteger', 2),
< 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
< 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,
---
> 'IsInteger', 3),
> 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 3),
> 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
131c125
< 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
---
> 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 3,
133c127
< 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
---
> 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
135,153c129,147
< 'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
< 'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
< 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2),
< 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2),
< 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2),
< 'FpOp1P4': ('FloatReg', 'sf', '(op1 + 4)', 'IsFloating', 2),
< 'FpOp1P5': ('FloatReg', 'sf', '(op1 + 5)', 'IsFloating', 2),
< 'FpOp1P6': ('FloatReg', 'sf', '(op1 + 6)', 'IsFloating', 2),
< 'FpOp1P7': ('FloatReg', 'sf', '(op1 + 7)', 'IsFloating', 2),
< 'FpOp1S0P0': ('FloatReg', 'sf', '(op1 + step * 0 + 0)', 'IsFloating', 2),
< 'FpOp1S0P1': ('FloatReg', 'sf', '(op1 + step * 0 + 1)', 'IsFloating', 2),
< 'FpOp1S1P0': ('FloatReg', 'sf', '(op1 + step * 1 + 0)', 'IsFloating', 2),
< 'FpOp1S1P1': ('FloatReg', 'sf', '(op1 + step * 1 + 1)', 'IsFloating', 2),
< 'FpOp1S2P0': ('FloatReg', 'sf', '(op1 + step * 2 + 0)', 'IsFloating', 2),
< 'FpOp1S2P1': ('FloatReg', 'sf', '(op1 + step * 2 + 1)', 'IsFloating', 2),
< 'FpOp1S3P0': ('FloatReg', 'sf', '(op1 + step * 3 + 0)', 'IsFloating', 2),
< 'FpOp1S3P1': ('FloatReg', 'sf', '(op1 + step * 3 + 1)', 'IsFloating', 2),
< 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),
< 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2,
---
> 'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3),
> 'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 3),
> 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 3),
> 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 3),
> 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 3),
> 'FpOp1P4': ('FloatReg', 'sf', '(op1 + 4)', 'IsFloating', 3),
> 'FpOp1P5': ('FloatReg', 'sf', '(op1 + 5)', 'IsFloating', 3),
> 'FpOp1P6': ('FloatReg', 'sf', '(op1 + 6)', 'IsFloating', 3),
> 'FpOp1P7': ('FloatReg', 'sf', '(op1 + 7)', 'IsFloating', 3),
> 'FpOp1S0P0': ('FloatReg', 'sf', '(op1 + step * 0 + 0)', 'IsFloating', 3),
> 'FpOp1S0P1': ('FloatReg', 'sf', '(op1 + step * 0 + 1)', 'IsFloating', 3),
> 'FpOp1S1P0': ('FloatReg', 'sf', '(op1 + step * 1 + 0)', 'IsFloating', 3),
> 'FpOp1S1P1': ('FloatReg', 'sf', '(op1 + step * 1 + 1)', 'IsFloating', 3),
> 'FpOp1S2P0': ('FloatReg', 'sf', '(op1 + step * 2 + 0)', 'IsFloating', 3),
> 'FpOp1S2P1': ('FloatReg', 'sf', '(op1 + step * 2 + 1)', 'IsFloating', 3),
> 'FpOp1S3P0': ('FloatReg', 'sf', '(op1 + step * 3 + 0)', 'IsFloating', 3),
> 'FpOp1S3P1': ('FloatReg', 'sf', '(op1 + step * 3 + 1)', 'IsFloating', 3),
> 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 3),
> 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 3,
155,160c149,154
< 'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
< 'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
< 'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2),
< 'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2),
< 'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2),
< 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2,
---
> 'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3),
> 'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 3),
> 'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 3),
> 'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 3),
> 'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 3),
> 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 3,
162c156
< 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2,
---
> 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 3,
164c158
< 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2,
---
> 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 3,
166c160
< 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2,
---
> 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 3,
168c162
< 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 2,
---
> 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 3,
170c164
< 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 2,
---
> 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 3,
173,178c167,172
< 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 2, maybePCRead, maybePCWrite),
< 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
< 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite),
< 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite),
< 'R7': ('IntReg', 'uw', '7', 'IsInteger', 2),
< 'R0': ('IntReg', 'uw', '0', 'IsInteger', 2),
---
> 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 3, maybePCRead, maybePCWrite),
> 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 3, maybePCRead, maybePCWrite),
> 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
> 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 3, maybePCRead, maybePCWrite),
> 'R7': ('IntReg', 'uw', '7', 'IsInteger', 3),
> 'R0': ('IntReg', 'uw', '0', 'IsInteger', 3),
180,181c174,175
< 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2),
< 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2),
---
> 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 3),
> 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 3),
184,185c178,179
< INTREG_ZERO : INTREG_CONDCODES''', None, 2),
< 'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 2),
---
> INTREG_ZERO : INTREG_CONDCODES''', None, 3),
> 'FpCondCodes': ('IntReg', 'uw', 'INTREG_FPCONDCODES', None, 3),
188,189c182,183
< 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite),
< 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2,
---
> 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 3, maybePCRead, maybePCWrite),
> 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 3,
191,193c185,187
< 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2),
< 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite),
< 'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 2, maybePCRead, maybePCWrite),
---
> 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 3),
> 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 3, maybePCRead, maybePCWrite),
> 'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 3, maybePCRead, maybePCWrite),
196,198c190,192
< 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2),
< 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
< 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2),
---
> 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 3),
> 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 3),
> 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 3),
201c195
< 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2),
---
> 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 3),
203,219c197,211
< 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1),
< 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 2),
< 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2),
< 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2),
< 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2),
< 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
< 'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 2),
< 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
< 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2),
< 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2),
< 'PC': ('PC', 'ud', None, None, 2),
< 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
< readNPC, writeNPC),
< 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
< readNPC, forceNPC),
< 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
< readNPC, writeIWNPC),
---
> 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 2),
> 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 3),
> 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 3),
> 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 3),
> 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 3),
> 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 3),
> 'Cpacr': ('ControlReg', 'uw', 'MISCREG_CPACR', (None, None, 'IsControl'), 3),
> 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 3),
> 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 3),
> 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 3),
> #PCS needs to have a sorting index (the number at the end) less than all
> #the integer registers which might update the PC. That way if the flag
> #bits of the pc state are updated and a branch happens through R15, the
> #updates are layered properly and the R15 update isn't lost.
> 'PCS': ('PCState', 'uw', None, (None, None, 'IsControl'), 0)