92a93,94
> 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 0,
> maybePCRead, maybePCWrite),
127,130d128
< #Destination register for load/store double instructions
< 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
< 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
<