78a79,84
> 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
> maybePCRead, maybePCWrite),
> 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
> maybePCRead, maybePCWrite),
> 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
> maybePCRead, maybePCWrite),