1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Copyright (c) 2007-2008 The Florida State University
15// All rights reserved.
16//
17// Redistribution and use in source and binary forms, with or without
18// modification, are permitted provided that the following conditions are
19// met: redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer;
21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
24// neither the name of the copyright holders nor the names of its
25// contributors may be used to endorse or promote products derived from
26// this software without specific prior written permission.
27//
28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : ('signed int', 8),
44 'ub' : ('unsigned int', 8),
45 'sh' : ('signed int', 16),
46 'uh' : ('unsigned int', 16),
47 'sw' : ('signed int', 32),
48 'uw' : ('unsigned int', 32),
49 'ud' : ('unsigned int', 64),
50 'tud' : ('twin64 int', 64),
51 'sf' : ('float', 32),
52 'df' : ('float', 64)
53}};
54
55let {{
56 maybePCRead = '''
57 ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybeAlignedPCRead = '''
60 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
61 xc->%(func)s(this, %(op_idx)s))
62 '''
63 maybePCWrite = '''
64 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
65 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66 '''
67 maybeIWPCWrite = '''
68 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
69 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
70 '''
71 maybeAIWPCWrite = '''
72 if (%(reg_idx)s == PCReg) {
73 bool thumb = THUMB;
74 if (thumb) {
75 setNextPC(xc, %(final_val)s);
76 } else {
77 setIWNextPC(xc, %(final_val)s);
78 }
79 } else {
80 xc->%(func)s(this, %(op_idx)s, %(final_val)s);
81 }
82 '''
83
84 #PCState operands need to have a sorting index (the number at the end)
85 #less than all the integer registers which might update the PC. That way
86 #if the flag bits of the pc state are updated and a branch happens through
87 #R15, the updates are layered properly and the R15 update isn't lost.
88 srtNormal = 5
89 srtCpsr = 4
90 srtBase = 3
91 srtPC = 2
92 srtMode = 1
93 srtEPC = 0
94
95 def floatReg(idx):
96 return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
97
98 def intReg(idx):
99 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
100 maybePCRead, maybePCWrite)
101
102 def intRegNPC(idx):
103 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
104
105 def intRegAPC(idx, id = srtNormal):
106 return ('IntReg', 'uw', idx, 'IsInteger', id,
107 maybeAlignedPCRead, maybePCWrite)
108
109 def intRegIWPC(idx):
110 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
111 maybePCRead, maybeIWPCWrite)
112
113 def intRegAIWPC(idx):
114 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
115 maybePCRead, maybeAIWPCWrite)
116
117 def intRegCC(idx):
118 return ('IntReg', 'uw', idx, None, srtNormal)
119
120 def cntrlReg(idx, id = srtNormal, type = 'uw'):
121 return ('ControlReg', type, idx, (None, None, 'IsControl'), id)
122
123 def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
124 return ('ControlReg', type, idx, None, id)
125
126 def pcStateReg(idx, id):
127 return ('PCState', 'uw', idx, (None, None, 'IsControl'), id)
128}};
129
130def operands {{
131 #Abstracted integer reg operands
132 'Dest': intReg('dest'),
133 'IWDest': intRegIWPC('dest'),
134 'AIWDest': intRegAIWPC('dest'),
135 'Dest2': intReg('dest2'),
136 'Result': intReg('result'),
137 'Base': intRegAPC('base', id = srtBase),
138 'Index': intReg('index'),
139 'Shift': intReg('shift'),
140 'Op1': intReg('op1'),
141 'Op2': intReg('op2'),
142 'Op3': intReg('op3'),
143 'Reg0': intReg('reg0'),
144 'Reg1': intReg('reg1'),
145 'Reg2': intReg('reg2'),
146 'Reg3': intReg('reg3'),
147
148 #Fixed index integer reg operands
149 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
150 'LR': intRegNPC('INTREG_LR'),
151 'R7': intRegNPC('7'),
152 # First four arguments are passed in registers
153 'R0': intRegNPC('0'),
154 'R1': intRegNPC('1'),
155 'R2': intRegNPC('2'),
156 'R3': intRegNPC('3'),
157
158 #Pseudo integer condition code registers
| 1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Copyright (c) 2007-2008 The Florida State University
15// All rights reserved.
16//
17// Redistribution and use in source and binary forms, with or without
18// modification, are permitted provided that the following conditions are
19// met: redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer;
21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
24// neither the name of the copyright holders nor the names of its
25// contributors may be used to endorse or promote products derived from
26// this software without specific prior written permission.
27//
28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : ('signed int', 8),
44 'ub' : ('unsigned int', 8),
45 'sh' : ('signed int', 16),
46 'uh' : ('unsigned int', 16),
47 'sw' : ('signed int', 32),
48 'uw' : ('unsigned int', 32),
49 'ud' : ('unsigned int', 64),
50 'tud' : ('twin64 int', 64),
51 'sf' : ('float', 32),
52 'df' : ('float', 64)
53}};
54
55let {{
56 maybePCRead = '''
57 ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybeAlignedPCRead = '''
60 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
61 xc->%(func)s(this, %(op_idx)s))
62 '''
63 maybePCWrite = '''
64 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
65 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66 '''
67 maybeIWPCWrite = '''
68 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
69 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
70 '''
71 maybeAIWPCWrite = '''
72 if (%(reg_idx)s == PCReg) {
73 bool thumb = THUMB;
74 if (thumb) {
75 setNextPC(xc, %(final_val)s);
76 } else {
77 setIWNextPC(xc, %(final_val)s);
78 }
79 } else {
80 xc->%(func)s(this, %(op_idx)s, %(final_val)s);
81 }
82 '''
83
84 #PCState operands need to have a sorting index (the number at the end)
85 #less than all the integer registers which might update the PC. That way
86 #if the flag bits of the pc state are updated and a branch happens through
87 #R15, the updates are layered properly and the R15 update isn't lost.
88 srtNormal = 5
89 srtCpsr = 4
90 srtBase = 3
91 srtPC = 2
92 srtMode = 1
93 srtEPC = 0
94
95 def floatReg(idx):
96 return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
97
98 def intReg(idx):
99 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
100 maybePCRead, maybePCWrite)
101
102 def intRegNPC(idx):
103 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
104
105 def intRegAPC(idx, id = srtNormal):
106 return ('IntReg', 'uw', idx, 'IsInteger', id,
107 maybeAlignedPCRead, maybePCWrite)
108
109 def intRegIWPC(idx):
110 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
111 maybePCRead, maybeIWPCWrite)
112
113 def intRegAIWPC(idx):
114 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
115 maybePCRead, maybeAIWPCWrite)
116
117 def intRegCC(idx):
118 return ('IntReg', 'uw', idx, None, srtNormal)
119
120 def cntrlReg(idx, id = srtNormal, type = 'uw'):
121 return ('ControlReg', type, idx, (None, None, 'IsControl'), id)
122
123 def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
124 return ('ControlReg', type, idx, None, id)
125
126 def pcStateReg(idx, id):
127 return ('PCState', 'uw', idx, (None, None, 'IsControl'), id)
128}};
129
130def operands {{
131 #Abstracted integer reg operands
132 'Dest': intReg('dest'),
133 'IWDest': intRegIWPC('dest'),
134 'AIWDest': intRegAIWPC('dest'),
135 'Dest2': intReg('dest2'),
136 'Result': intReg('result'),
137 'Base': intRegAPC('base', id = srtBase),
138 'Index': intReg('index'),
139 'Shift': intReg('shift'),
140 'Op1': intReg('op1'),
141 'Op2': intReg('op2'),
142 'Op3': intReg('op3'),
143 'Reg0': intReg('reg0'),
144 'Reg1': intReg('reg1'),
145 'Reg2': intReg('reg2'),
146 'Reg3': intReg('reg3'),
147
148 #Fixed index integer reg operands
149 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
150 'LR': intRegNPC('INTREG_LR'),
151 'R7': intRegNPC('7'),
152 # First four arguments are passed in registers
153 'R0': intRegNPC('0'),
154 'R1': intRegNPC('1'),
155 'R2': intRegNPC('2'),
156 'R3': intRegNPC('3'),
157
158 #Pseudo integer condition code registers
|
163 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'),
164
165 #Abstracted floating point reg operands
166 'FpDest': floatReg('(dest + 0)'),
167 'FpDestP0': floatReg('(dest + 0)'),
168 'FpDestP1': floatReg('(dest + 1)'),
169 'FpDestP2': floatReg('(dest + 2)'),
170 'FpDestP3': floatReg('(dest + 3)'),
171 'FpDestP4': floatReg('(dest + 4)'),
172 'FpDestP5': floatReg('(dest + 5)'),
173 'FpDestP6': floatReg('(dest + 6)'),
174 'FpDestP7': floatReg('(dest + 7)'),
175 'FpDestS0P0': floatReg('(dest + step * 0 + 0)'),
176 'FpDestS0P1': floatReg('(dest + step * 0 + 1)'),
177 'FpDestS1P0': floatReg('(dest + step * 1 + 0)'),
178 'FpDestS1P1': floatReg('(dest + step * 1 + 1)'),
179 'FpDestS2P0': floatReg('(dest + step * 2 + 0)'),
180 'FpDestS2P1': floatReg('(dest + step * 2 + 1)'),
181 'FpDestS3P0': floatReg('(dest + step * 3 + 0)'),
182 'FpDestS3P1': floatReg('(dest + step * 3 + 1)'),
183
184 'FpDest2': floatReg('(dest2 + 0)'),
185 'FpDest2P0': floatReg('(dest2 + 0)'),
186 'FpDest2P1': floatReg('(dest2 + 1)'),
187 'FpDest2P2': floatReg('(dest2 + 2)'),
188 'FpDest2P3': floatReg('(dest2 + 3)'),
189
190 'FpOp1': floatReg('(op1 + 0)'),
191 'FpOp1P0': floatReg('(op1 + 0)'),
192 'FpOp1P1': floatReg('(op1 + 1)'),
193 'FpOp1P2': floatReg('(op1 + 2)'),
194 'FpOp1P3': floatReg('(op1 + 3)'),
195 'FpOp1P4': floatReg('(op1 + 4)'),
196 'FpOp1P5': floatReg('(op1 + 5)'),
197 'FpOp1P6': floatReg('(op1 + 6)'),
198 'FpOp1P7': floatReg('(op1 + 7)'),
199 'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'),
200 'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'),
201 'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'),
202 'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'),
203 'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'),
204 'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'),
205 'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'),
206 'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),
207
208 'FpOp2': floatReg('(op2 + 0)'),
209 'FpOp2P0': floatReg('(op2 + 0)'),
210 'FpOp2P1': floatReg('(op2 + 1)'),
211 'FpOp2P2': floatReg('(op2 + 2)'),
212 'FpOp2P3': floatReg('(op2 + 3)'),
213
214 #Abstracted control reg operands
215 'MiscDest': cntrlReg('dest'),
216 'MiscOp1': cntrlReg('op1'),
217
218 #Fixed index control regs
219 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
220 'Spsr': cntrlRegNC('MISCREG_SPSR'),
221 'Fpsr': cntrlRegNC('MISCREG_FPSR'),
222 'Fpsid': cntrlRegNC('MISCREG_FPSID'),
223 'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
224 'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
225 'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
226 'Cpacr': cntrlReg('MISCREG_CPACR'),
227 'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
228 'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
229 'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
230 'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
231
232 #Register fields for microops
233 'URa' : intReg('ura'),
234 'IWRa' : intRegIWPC('ura'),
235 'Fa' : floatReg('ura'),
236 'URb' : intReg('urb'),
237 'URc' : intReg('urc'),
238
239 #Memory Operand
240 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
241
242 #PCState fields
243 'PC': pcStateReg('instPC', srtPC),
244 'NPC': pcStateReg('instNPC', srtPC),
245 'pNPC': pcStateReg('instNPC', srtEPC),
246 'IWNPC': pcStateReg('instIWNPC', srtPC),
247 'Thumb': pcStateReg('thumb', srtPC),
248 'NextThumb': pcStateReg('nextThumb', srtMode),
249 'NextJazelle': pcStateReg('nextJazelle', srtMode),
250 'NextItState': pcStateReg('nextItstate', srtMode),
251 'Itstate': pcStateReg('itstate', srtMode),
252
253 #Register operands depending on a field in the instruction encoding. These
254 #should be avoided since they may not be portable across different
255 #encodings of the same instruction.
256 'Rd': intReg('RD'),
257 'Rm': intReg('RM'),
258 'Rs': intReg('RS'),
259 'Rn': intReg('RN'),
260 'Rt': intReg('RT')
261}};
| 165 'FpCondCodes': intRegCC('INTREG_FPCONDCODES'),
166
167 #Abstracted floating point reg operands
168 'FpDest': floatReg('(dest + 0)'),
169 'FpDestP0': floatReg('(dest + 0)'),
170 'FpDestP1': floatReg('(dest + 1)'),
171 'FpDestP2': floatReg('(dest + 2)'),
172 'FpDestP3': floatReg('(dest + 3)'),
173 'FpDestP4': floatReg('(dest + 4)'),
174 'FpDestP5': floatReg('(dest + 5)'),
175 'FpDestP6': floatReg('(dest + 6)'),
176 'FpDestP7': floatReg('(dest + 7)'),
177 'FpDestS0P0': floatReg('(dest + step * 0 + 0)'),
178 'FpDestS0P1': floatReg('(dest + step * 0 + 1)'),
179 'FpDestS1P0': floatReg('(dest + step * 1 + 0)'),
180 'FpDestS1P1': floatReg('(dest + step * 1 + 1)'),
181 'FpDestS2P0': floatReg('(dest + step * 2 + 0)'),
182 'FpDestS2P1': floatReg('(dest + step * 2 + 1)'),
183 'FpDestS3P0': floatReg('(dest + step * 3 + 0)'),
184 'FpDestS3P1': floatReg('(dest + step * 3 + 1)'),
185
186 'FpDest2': floatReg('(dest2 + 0)'),
187 'FpDest2P0': floatReg('(dest2 + 0)'),
188 'FpDest2P1': floatReg('(dest2 + 1)'),
189 'FpDest2P2': floatReg('(dest2 + 2)'),
190 'FpDest2P3': floatReg('(dest2 + 3)'),
191
192 'FpOp1': floatReg('(op1 + 0)'),
193 'FpOp1P0': floatReg('(op1 + 0)'),
194 'FpOp1P1': floatReg('(op1 + 1)'),
195 'FpOp1P2': floatReg('(op1 + 2)'),
196 'FpOp1P3': floatReg('(op1 + 3)'),
197 'FpOp1P4': floatReg('(op1 + 4)'),
198 'FpOp1P5': floatReg('(op1 + 5)'),
199 'FpOp1P6': floatReg('(op1 + 6)'),
200 'FpOp1P7': floatReg('(op1 + 7)'),
201 'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'),
202 'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'),
203 'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'),
204 'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'),
205 'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'),
206 'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'),
207 'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'),
208 'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),
209
210 'FpOp2': floatReg('(op2 + 0)'),
211 'FpOp2P0': floatReg('(op2 + 0)'),
212 'FpOp2P1': floatReg('(op2 + 1)'),
213 'FpOp2P2': floatReg('(op2 + 2)'),
214 'FpOp2P3': floatReg('(op2 + 3)'),
215
216 #Abstracted control reg operands
217 'MiscDest': cntrlReg('dest'),
218 'MiscOp1': cntrlReg('op1'),
219
220 #Fixed index control regs
221 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
222 'Spsr': cntrlRegNC('MISCREG_SPSR'),
223 'Fpsr': cntrlRegNC('MISCREG_FPSR'),
224 'Fpsid': cntrlRegNC('MISCREG_FPSID'),
225 'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
226 'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
227 'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
228 'Cpacr': cntrlReg('MISCREG_CPACR'),
229 'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
230 'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
231 'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
232 'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
233
234 #Register fields for microops
235 'URa' : intReg('ura'),
236 'IWRa' : intRegIWPC('ura'),
237 'Fa' : floatReg('ura'),
238 'URb' : intReg('urb'),
239 'URc' : intReg('urc'),
240
241 #Memory Operand
242 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
243
244 #PCState fields
245 'PC': pcStateReg('instPC', srtPC),
246 'NPC': pcStateReg('instNPC', srtPC),
247 'pNPC': pcStateReg('instNPC', srtEPC),
248 'IWNPC': pcStateReg('instIWNPC', srtPC),
249 'Thumb': pcStateReg('thumb', srtPC),
250 'NextThumb': pcStateReg('nextThumb', srtMode),
251 'NextJazelle': pcStateReg('nextJazelle', srtMode),
252 'NextItState': pcStateReg('nextItstate', srtMode),
253 'Itstate': pcStateReg('itstate', srtMode),
254
255 #Register operands depending on a field in the instruction encoding. These
256 #should be avoided since they may not be portable across different
257 #encodings of the same instruction.
258 'Rd': intReg('RD'),
259 'Rm': intReg('RM'),
260 'Rs': intReg('RS'),
261 'Rn': intReg('RN'),
262 'Rt': intReg('RT')
263}};
|