1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Copyright (c) 2007-2008 The Florida State University
15// All rights reserved.
16//
17// Redistribution and use in source and binary forms, with or without
18// modification, are permitted provided that the following conditions are
19// met: redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer;
21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
24// neither the name of the copyright holders nor the names of its
25// contributors may be used to endorse or promote products derived from
26// this software without specific prior written permission.
27//
28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : ('signed int', 8),
44 'ub' : ('unsigned int', 8),
45 'sh' : ('signed int', 16),
46 'uh' : ('unsigned int', 16),
47 'sw' : ('signed int', 32),
48 'uw' : ('unsigned int', 32),
49 'ud' : ('unsigned int', 64),
| 1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Copyright (c) 2007-2008 The Florida State University
15// All rights reserved.
16//
17// Redistribution and use in source and binary forms, with or without
18// modification, are permitted provided that the following conditions are
19// met: redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer;
21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
24// neither the name of the copyright holders nor the names of its
25// contributors may be used to endorse or promote products derived from
26// this software without specific prior written permission.
27//
28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : ('signed int', 8),
44 'ub' : ('unsigned int', 8),
45 'sh' : ('signed int', 16),
46 'uh' : ('unsigned int', 16),
47 'sw' : ('signed int', 32),
48 'uw' : ('unsigned int', 32),
49 'ud' : ('unsigned int', 64),
|
| 50 'tud' : ('twin64 int', 64),
|
50 'sf' : ('float', 32),
51 'df' : ('float', 64)
52}};
53
54let {{
55 maybePCRead = '''
56 ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
57 xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybeAlignedPCRead = '''
60 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) :
61 xc->%(func)s(this, %(op_idx)s))
62 '''
63 maybePCWrite = '''
64 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
65 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66 '''
67 maybeIWPCWrite = '''
68 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
69 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
70 '''
71 maybeAIWPCWrite = '''
72 if (%(reg_idx)s == PCReg) {
73 bool thumb = THUMB;
74 if (thumb) {
75 setNextPC(xc, %(final_val)s);
76 } else {
77 setIWNextPC(xc, %(final_val)s);
78 }
79 } else {
80 xc->%(func)s(this, %(op_idx)s, %(final_val)s);
81 }
82 '''
83
84 readNPC = 'xc->readNextPC() & ~PcModeMask'
85 writeNPC = 'setNextPC(xc, %(final_val)s)'
86 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
87 forceNPC = 'xc->setNextPC(%(final_val)s)'
88}};
89
90def operands {{
91 #Abstracted integer reg operands
92 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
93 maybePCRead, maybePCWrite),
94 'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
95 'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
96 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2),
97 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2),
98 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2),
| 51 'sf' : ('float', 32),
52 'df' : ('float', 64)
53}};
54
55let {{
56 maybePCRead = '''
57 ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
58 xc->%(func)s(this, %(op_idx)s))
59 '''
60 maybeAlignedPCRead = '''
61 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc) & ~PcModeMask, 4)) :
62 xc->%(func)s(this, %(op_idx)s))
63 '''
64 maybePCWrite = '''
65 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
66 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
67 '''
68 maybeIWPCWrite = '''
69 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
70 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
71 '''
72 maybeAIWPCWrite = '''
73 if (%(reg_idx)s == PCReg) {
74 bool thumb = THUMB;
75 if (thumb) {
76 setNextPC(xc, %(final_val)s);
77 } else {
78 setIWNextPC(xc, %(final_val)s);
79 }
80 } else {
81 xc->%(func)s(this, %(op_idx)s, %(final_val)s);
82 }
83 '''
84
85 readNPC = 'xc->readNextPC() & ~PcModeMask'
86 writeNPC = 'setNextPC(xc, %(final_val)s)'
87 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
88 forceNPC = 'xc->setNextPC(%(final_val)s)'
89}};
90
91def operands {{
92 #Abstracted integer reg operands
93 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
94 maybePCRead, maybePCWrite),
95 'FpDest': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
96 'FpDestP0': ('FloatReg', 'sf', '(dest + 0)', 'IsFloating', 2),
97 'FpDestP1': ('FloatReg', 'sf', '(dest + 1)', 'IsFloating', 2),
98 'FpDestP2': ('FloatReg', 'sf', '(dest + 2)', 'IsFloating', 2),
99 'FpDestP3': ('FloatReg', 'sf', '(dest + 3)', 'IsFloating', 2),
|
| 100 'FpDestP4': ('FloatReg', 'sf', '(dest + 4)', 'IsFloating', 2),
101 'FpDestP5': ('FloatReg', 'sf', '(dest + 5)', 'IsFloating', 2),
102 'FpDestP6': ('FloatReg', 'sf', '(dest + 6)', 'IsFloating', 2),
103 'FpDestP7': ('FloatReg', 'sf', '(dest + 7)', 'IsFloating', 2),
104 'FpDestS0P0': ('FloatReg', 'sf', '(dest + step * 0 + 0)', 'IsFloating', 2),
105 'FpDestS0P1': ('FloatReg', 'sf', '(dest + step * 0 + 1)', 'IsFloating', 2),
106 'FpDestS1P0': ('FloatReg', 'sf', '(dest + step * 1 + 0)', 'IsFloating', 2),
107 'FpDestS1P1': ('FloatReg', 'sf', '(dest + step * 1 + 1)', 'IsFloating', 2),
108 'FpDestS2P0': ('FloatReg', 'sf', '(dest + step * 2 + 0)', 'IsFloating', 2),
109 'FpDestS2P1': ('FloatReg', 'sf', '(dest + step * 2 + 1)', 'IsFloating', 2),
110 'FpDestS3P0': ('FloatReg', 'sf', '(dest + step * 3 + 0)', 'IsFloating', 2),
111 'FpDestS3P1': ('FloatReg', 'sf', '(dest + step * 3 + 1)', 'IsFloating', 2),
|
99 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
100 maybePCRead, maybePCWrite),
101 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
102 maybePCRead, maybePCWrite),
103 'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
104 'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
105 'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2),
106 'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2),
107 'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 2),
108 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
109 maybePCRead, maybeIWPCWrite),
110 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
111 maybePCRead, maybeAIWPCWrite),
112 'SpMode': ('IntReg', 'uw',
113 'intRegInMode((OperatingMode)regMode, INTREG_SP)',
114 'IsInteger', 2),
115 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
116 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,
117 maybeAlignedPCRead, maybePCWrite),
118 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
119 maybePCRead, maybePCWrite),
120 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
121 maybePCRead, maybePCWrite),
122 'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
123 'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
124 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2),
125 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2),
126 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2),
| 112 'Result': ('IntReg', 'uw', 'result', 'IsInteger', 2,
113 maybePCRead, maybePCWrite),
114 'Dest2': ('IntReg', 'uw', 'dest2', 'IsInteger', 2,
115 maybePCRead, maybePCWrite),
116 'FpDest2': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
117 'FpDest2P0': ('FloatReg', 'sf', '(dest2 + 0)', 'IsFloating', 2),
118 'FpDest2P1': ('FloatReg', 'sf', '(dest2 + 1)', 'IsFloating', 2),
119 'FpDest2P2': ('FloatReg', 'sf', '(dest2 + 2)', 'IsFloating', 2),
120 'FpDest2P3': ('FloatReg', 'sf', '(dest2 + 3)', 'IsFloating', 2),
121 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
122 maybePCRead, maybeIWPCWrite),
123 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 2,
124 maybePCRead, maybeAIWPCWrite),
125 'SpMode': ('IntReg', 'uw',
126 'intRegInMode((OperatingMode)regMode, INTREG_SP)',
127 'IsInteger', 2),
128 'MiscDest': ('ControlReg', 'uw', 'dest', (None, None, 'IsControl'), 2),
129 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 0,
130 maybeAlignedPCRead, maybePCWrite),
131 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
132 maybePCRead, maybePCWrite),
133 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 2,
134 maybePCRead, maybePCWrite),
135 'FpOp1': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
136 'FpOp1P0': ('FloatReg', 'sf', '(op1 + 0)', 'IsFloating', 2),
137 'FpOp1P1': ('FloatReg', 'sf', '(op1 + 1)', 'IsFloating', 2),
138 'FpOp1P2': ('FloatReg', 'sf', '(op1 + 2)', 'IsFloating', 2),
139 'FpOp1P3': ('FloatReg', 'sf', '(op1 + 3)', 'IsFloating', 2),
|
| 140 'FpOp1P4': ('FloatReg', 'sf', '(op1 + 4)', 'IsFloating', 2),
141 'FpOp1P5': ('FloatReg', 'sf', '(op1 + 5)', 'IsFloating', 2),
142 'FpOp1P6': ('FloatReg', 'sf', '(op1 + 6)', 'IsFloating', 2),
143 'FpOp1P7': ('FloatReg', 'sf', '(op1 + 7)', 'IsFloating', 2),
144 'FpOp1S0P0': ('FloatReg', 'sf', '(op1 + step * 0 + 0)', 'IsFloating', 2),
145 'FpOp1S0P1': ('FloatReg', 'sf', '(op1 + step * 0 + 1)', 'IsFloating', 2),
146 'FpOp1S1P0': ('FloatReg', 'sf', '(op1 + step * 1 + 0)', 'IsFloating', 2),
147 'FpOp1S1P1': ('FloatReg', 'sf', '(op1 + step * 1 + 1)', 'IsFloating', 2),
148 'FpOp1S2P0': ('FloatReg', 'sf', '(op1 + step * 2 + 0)', 'IsFloating', 2),
149 'FpOp1S2P1': ('FloatReg', 'sf', '(op1 + step * 2 + 1)', 'IsFloating', 2),
150 'FpOp1S3P0': ('FloatReg', 'sf', '(op1 + step * 3 + 0)', 'IsFloating', 2),
151 'FpOp1S3P1': ('FloatReg', 'sf', '(op1 + step * 3 + 1)', 'IsFloating', 2),
|
127 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),
128 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2,
129 maybePCRead, maybePCWrite),
130 'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
131 'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
132 'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2),
133 'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2),
134 'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2),
135 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2,
136 maybePCRead, maybePCWrite),
137 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2,
138 maybePCRead, maybePCWrite),
139 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2,
140 maybePCRead, maybePCWrite),
141 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2,
142 maybePCRead, maybePCWrite),
143 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 2,
144 maybePCRead, maybePCWrite),
145 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 2,
146 maybePCRead, maybePCWrite),
147 #General Purpose Integer Reg Operands
148 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 2, maybePCRead, maybePCWrite),
149 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
150 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite),
151 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite),
152 'R7': ('IntReg', 'uw', '7', 'IsInteger', 2),
153 'R0': ('IntReg', 'uw', '0', 'IsInteger', 2),
154
155 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2),
156 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2),
157 'OptCondCodes': ('IntReg', 'uw',
158 '''(condCode == COND_AL || condCode == COND_UC) ?
159 INTREG_ZERO : INTREG_CONDCODES''', None, 2),
160
161 #Register fields for microops
162 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite),
163 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2,
164 maybePCRead, maybeIWPCWrite),
165 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2),
166 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite),
| 152 'MiscOp1': ('ControlReg', 'uw', 'op1', (None, None, 'IsControl'), 2),
153 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 2,
154 maybePCRead, maybePCWrite),
155 'FpOp2': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
156 'FpOp2P0': ('FloatReg', 'sf', '(op2 + 0)', 'IsFloating', 2),
157 'FpOp2P1': ('FloatReg', 'sf', '(op2 + 1)', 'IsFloating', 2),
158 'FpOp2P2': ('FloatReg', 'sf', '(op2 + 2)', 'IsFloating', 2),
159 'FpOp2P3': ('FloatReg', 'sf', '(op2 + 3)', 'IsFloating', 2),
160 'Op3': ('IntReg', 'uw', 'op3', 'IsInteger', 2,
161 maybePCRead, maybePCWrite),
162 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 2,
163 maybePCRead, maybePCWrite),
164 'Reg0': ('IntReg', 'uw', 'reg0', 'IsInteger', 2,
165 maybePCRead, maybePCWrite),
166 'Reg1': ('IntReg', 'uw', 'reg1', 'IsInteger', 2,
167 maybePCRead, maybePCWrite),
168 'Reg2': ('IntReg', 'uw', 'reg2', 'IsInteger', 2,
169 maybePCRead, maybePCWrite),
170 'Reg3': ('IntReg', 'uw', 'reg3', 'IsInteger', 2,
171 maybePCRead, maybePCWrite),
172 #General Purpose Integer Reg Operands
173 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 2, maybePCRead, maybePCWrite),
174 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
175 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 2, maybePCRead, maybePCWrite),
176 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 2, maybePCRead, maybePCWrite),
177 'R7': ('IntReg', 'uw', '7', 'IsInteger', 2),
178 'R0': ('IntReg', 'uw', '0', 'IsInteger', 2),
179
180 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 2),
181 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 2),
182 'OptCondCodes': ('IntReg', 'uw',
183 '''(condCode == COND_AL || condCode == COND_UC) ?
184 INTREG_ZERO : INTREG_CONDCODES''', None, 2),
185
186 #Register fields for microops
187 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 2, maybePCRead, maybePCWrite),
188 'IWRa' : ('IntReg', 'uw', 'ura', 'IsInteger', 2,
189 maybePCRead, maybeIWPCWrite),
190 'Fa' : ('FloatReg', 'sf', 'ura', 'IsFloating', 2),
191 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 2, maybePCRead, maybePCWrite),
|
| 192 'Rc' : ('IntReg', 'uw', 'urc', 'IsInteger', 2, maybePCRead, maybePCWrite),
|
167
168 #General Purpose Floating Point Reg Operands
169 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2),
170 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
171 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2),
172
173 #Memory Operand
174 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2),
175
176 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1),
177 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 2),
178 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2),
179 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2),
180 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2),
181 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
182 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
183 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2),
184 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2),
185 'PC': ('PC', 'ud', None, None, 2),
186 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
187 readNPC, writeNPC),
188 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
189 readNPC, forceNPC),
190 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
191 readNPC, writeIWNPC),
192}};
| 193
194 #General Purpose Floating Point Reg Operands
195 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 2),
196 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 2),
197 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 2),
198
199 #Memory Operand
200 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 2),
201
202 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 1),
203 'Itstate': ('ControlReg', 'ub', 'MISCREG_ITSTATE', None, 2),
204 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 2),
205 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 2),
206 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 2),
207 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 2),
208 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 2),
209 'Sctlr': ('ControlReg', 'uw', 'MISCREG_SCTLR', None, 2),
210 'SevMailbox': ('ControlReg', 'uw', 'MISCREG_SEV_MAILBOX', None, 2),
211 'PC': ('PC', 'ud', None, None, 2),
212 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
213 readNPC, writeNPC),
214 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
215 readNPC, forceNPC),
216 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 2,
217 readNPC, writeIWNPC),
218}};
|