1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Copyright (c) 2007-2008 The Florida State University
15// All rights reserved.
16//
17// Redistribution and use in source and binary forms, with or without
18// modification, are permitted provided that the following conditions are
19// met: redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer;
21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
24// neither the name of the copyright holders nor the names of its
25// contributors may be used to endorse or promote products derived from
26// this software without specific prior written permission.
27//
28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : ('signed int', 8),
44 'ub' : ('unsigned int', 8),
45 'sh' : ('signed int', 16),
46 'uh' : ('unsigned int', 16),
47 'sw' : ('signed int', 32),
48 'uw' : ('unsigned int', 32),
49 'ud' : ('unsigned int', 64),
50 'sf' : ('float', 32),
51 'df' : ('float', 64)
52}};
53
54let {{
55 maybePCRead = '''
56 ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
57 xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybePCWrite = '''
60 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
61 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62 '''
63 maybeIWPCWrite = '''
64 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
65 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66 '''
67
68 readNPC = 'xc->readNextPC() & ~PcModeMask'
69 writeNPC = 'setNextPC(xc, %(final_val)s)'
70 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
71 forceNPC = 'xc->setNextPC(%(final_val)s)'
72}};
73
74def operands {{
75 #Abstracted integer reg operands
76 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
77 maybePCRead, maybePCWrite),
78 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
79 maybePCRead, maybeIWPCWrite),
80 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
81 maybePCRead, maybeIWPCWrite),
82 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
83 maybePCRead, maybePCWrite),
84 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
85 maybePCRead, maybePCWrite),
86 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
87 maybePCRead, maybePCWrite),
88 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
89 maybePCRead, maybePCWrite),
90 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
91 maybePCRead, maybePCWrite),
| 1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Copyright (c) 2007-2008 The Florida State University
15// All rights reserved.
16//
17// Redistribution and use in source and binary forms, with or without
18// modification, are permitted provided that the following conditions are
19// met: redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer;
21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
24// neither the name of the copyright holders nor the names of its
25// contributors may be used to endorse or promote products derived from
26// this software without specific prior written permission.
27//
28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : ('signed int', 8),
44 'ub' : ('unsigned int', 8),
45 'sh' : ('signed int', 16),
46 'uh' : ('unsigned int', 16),
47 'sw' : ('signed int', 32),
48 'uw' : ('unsigned int', 32),
49 'ud' : ('unsigned int', 64),
50 'sf' : ('float', 32),
51 'df' : ('float', 64)
52}};
53
54let {{
55 maybePCRead = '''
56 ((%(reg_idx)s == PCReg) ? (readPC(xc) & ~PcModeMask) :
57 xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybePCWrite = '''
60 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
61 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62 '''
63 maybeIWPCWrite = '''
64 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
65 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
66 '''
67
68 readNPC = 'xc->readNextPC() & ~PcModeMask'
69 writeNPC = 'setNextPC(xc, %(final_val)s)'
70 writeIWNPC = 'setIWNextPC(xc, %(final_val)s)'
71 forceNPC = 'xc->setNextPC(%(final_val)s)'
72}};
73
74def operands {{
75 #Abstracted integer reg operands
76 'Dest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
77 maybePCRead, maybePCWrite),
78 'IWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
79 maybePCRead, maybeIWPCWrite),
80 'AIWDest': ('IntReg', 'uw', 'dest', 'IsInteger', 0,
81 maybePCRead, maybeIWPCWrite),
82 'Base': ('IntReg', 'uw', 'base', 'IsInteger', 1,
83 maybePCRead, maybePCWrite),
84 'Index': ('IntReg', 'uw', 'index', 'IsInteger', 2,
85 maybePCRead, maybePCWrite),
86 'Op1': ('IntReg', 'uw', 'op1', 'IsInteger', 3,
87 maybePCRead, maybePCWrite),
88 'Op2': ('IntReg', 'uw', 'op2', 'IsInteger', 4,
89 maybePCRead, maybePCWrite),
90 'Shift': ('IntReg', 'uw', 'shift', 'IsInteger', 5,
91 maybePCRead, maybePCWrite),
|
92 #General Purpose Integer Reg Operands
93 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
94 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
95 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
96 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
97 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
98 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
99
100 #Destination register for load/store double instructions
101 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
102 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
103
104 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
105 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
106 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
107 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),
108
109 #Register fields for microops
110 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
111 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
112
113 #General Purpose Floating Point Reg Operands
114 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
115 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
116 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
117
118 #Memory Operand
119 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
120
121 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
122 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
123 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
124 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
125 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
126 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
127 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
128 readNPC, writeNPC),
129 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
130 readNPC, forceNPC),
131 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
132 readNPC, writeIWNPC),
133}};
| 100 #General Purpose Integer Reg Operands
101 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
102 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
103 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
104 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
105 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
106 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
107
108 #Destination register for load/store double instructions
109 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
110 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
111
112 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
113 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
114 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
115 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),
116
117 #Register fields for microops
118 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
119 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
120
121 #General Purpose Floating Point Reg Operands
122 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
123 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
124 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
125
126 #Memory Operand
127 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
128
129 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
130 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
131 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
132 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
133 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
134 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
135 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
136 readNPC, writeNPC),
137 'FNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
138 readNPC, forceNPC),
139 'IWNPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
140 readNPC, writeIWNPC),
141}};
|