1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Copyright (c) 2007-2008 The Florida State University
15// All rights reserved.
16//
17// Redistribution and use in source and binary forms, with or without
18// modification, are permitted provided that the following conditions are
19// met: redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer;
21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
24// neither the name of the copyright holders nor the names of its
25// contributors may be used to endorse or promote products derived from
26// this software without specific prior written permission.
27//
28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : ('signed int', 8),
44 'ub' : ('unsigned int', 8),
45 'sh' : ('signed int', 16),
46 'uh' : ('unsigned int', 16),
47 'sw' : ('signed int', 32),
48 'uw' : ('unsigned int', 32),
49 'ud' : ('unsigned int', 64),
50 'sf' : ('float', 32),
51 'df' : ('float', 64)
52}};
53
54let {{
55 maybePCRead = '''
56 ((%(reg_idx)s == PCReg) ? ((xc->readPC() & ~PcModeMask) + 8) :
57 xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybePCWrite = '''
60 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
61 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62 '''
63
64 readPC = 'xc->readPC() & ~PcModeMask'
65 writePC = 'setPC(xc, %(final_val)s)'
66
67 readNPC = 'xc->readNextPC() & ~PcModeMask'
68 writeNPC = 'setNextPC(xc, %(final_val)s)'
69}};
70
71def operands {{
| 1// -*- mode:c++ -*-
2// Copyright (c) 2010 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Copyright (c) 2007-2008 The Florida State University
15// All rights reserved.
16//
17// Redistribution and use in source and binary forms, with or without
18// modification, are permitted provided that the following conditions are
19// met: redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer;
21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
24// neither the name of the copyright holders nor the names of its
25// contributors may be used to endorse or promote products derived from
26// this software without specific prior written permission.
27//
28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : ('signed int', 8),
44 'ub' : ('unsigned int', 8),
45 'sh' : ('signed int', 16),
46 'uh' : ('unsigned int', 16),
47 'sw' : ('signed int', 32),
48 'uw' : ('unsigned int', 32),
49 'ud' : ('unsigned int', 64),
50 'sf' : ('float', 32),
51 'df' : ('float', 64)
52}};
53
54let {{
55 maybePCRead = '''
56 ((%(reg_idx)s == PCReg) ? ((xc->readPC() & ~PcModeMask) + 8) :
57 xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybePCWrite = '''
60 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
61 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62 '''
63
64 readPC = 'xc->readPC() & ~PcModeMask'
65 writePC = 'setPC(xc, %(final_val)s)'
66
67 readNPC = 'xc->readNextPC() & ~PcModeMask'
68 writeNPC = 'setNextPC(xc, %(final_val)s)'
69}};
70
71def operands {{
|
72 #General Purpose Integer Reg Operands
73 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
74 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
75 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
76 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
77 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
78 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
79
80 #Destination register for load/store double instructions
81 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
82 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
83
84 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
85 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
86 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
87 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),
88
89 #Register fields for microops
90 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
91 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
92
93 #General Purpose Floating Point Reg Operands
94 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
95 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
96 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
97
98 #Memory Operand
99 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
100
101 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
102 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
103 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
104 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
105 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
106 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
107 'PC': ('PC', 'ud', None, (None, None, 'IsControl'), 50,
108 readPC, writePC),
109 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
110 readNPC, writeNPC),
111}};
| 79 #General Purpose Integer Reg Operands
80 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
81 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
82 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
83 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
84 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
85 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
86
87 #Destination register for load/store double instructions
88 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
89 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
90
91 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
92 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
93 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
94 'CondCodes': ('IntReg', 'uw', 'INTREG_CONDCODES', None, 10),
95
96 #Register fields for microops
97 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
98 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
99
100 #General Purpose Floating Point Reg Operands
101 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
102 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
103 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
104
105 #Memory Operand
106 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
107
108 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
109 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
110 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
111 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
112 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
113 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
114 'PC': ('PC', 'ud', None, (None, None, 'IsControl'), 50,
115 readPC, writePC),
116 'NPC': ('NPC', 'ud', None, (None, None, 'IsControl'), 51,
117 readNPC, writeNPC),
118}};
|