3// Copyright (c) 2007-2008 The Florida State University
4// All rights reserved.
5//
6// Redistribution and use in source and binary forms, with or without
7// modification, are permitted provided that the following conditions are
8// met: redistributions of source code must retain the above copyright
9// notice, this list of conditions and the following disclaimer;
10// redistributions in binary form must reproduce the above copyright
11// notice, this list of conditions and the following disclaimer in the
12// documentation and/or other materials provided with the distribution;
13// neither the name of the copyright holders nor the names of its
14// contributors may be used to endorse or promote products derived from
15// this software without specific prior written permission.
16//
17// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28//
29// Authors: Stephen Hines
30
31def operand_types {{
32 'sb' : ('signed int', 8),
33 'ub' : ('unsigned int', 8),
34 'sh' : ('signed int', 16),
35 'uh' : ('unsigned int', 16),
36 'sw' : ('signed int', 32),
37 'uw' : ('unsigned int', 32),
38 'ud' : ('unsigned int', 64),
39 'sf' : ('float', 32),
40 'df' : ('float', 64)
41}};
42
43let {{
44 maybePCRead = '''
45 ((%(reg_idx)s == PCReg) ? (xc->readPC() + 8) :
46 xc->%(func)s(this, %(op_idx)s))
47 '''
48 maybePCWrite = '''
49 ((%(reg_idx)s == PCReg) ? xc->setNextPC(%(final_val)s) :
50 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
51 '''
52}};
53
54def operands {{
55 #General Purpose Integer Reg Operands
56 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
57 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
58 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
59 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
60 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
61 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
62
63 #Destination register for load/store double instructions
64 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
65 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
66
67 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
68 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
69 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
| 14// Copyright (c) 2007-2008 The Florida State University
15// All rights reserved.
16//
17// Redistribution and use in source and binary forms, with or without
18// modification, are permitted provided that the following conditions are
19// met: redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer;
21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
24// neither the name of the copyright holders nor the names of its
25// contributors may be used to endorse or promote products derived from
26// this software without specific prior written permission.
27//
28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : ('signed int', 8),
44 'ub' : ('unsigned int', 8),
45 'sh' : ('signed int', 16),
46 'uh' : ('unsigned int', 16),
47 'sw' : ('signed int', 32),
48 'uw' : ('unsigned int', 32),
49 'ud' : ('unsigned int', 64),
50 'sf' : ('float', 32),
51 'df' : ('float', 64)
52}};
53
54let {{
55 maybePCRead = '''
56 ((%(reg_idx)s == PCReg) ? (xc->readPC() + 8) :
57 xc->%(func)s(this, %(op_idx)s))
58 '''
59 maybePCWrite = '''
60 ((%(reg_idx)s == PCReg) ? xc->setNextPC(%(final_val)s) :
61 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
62 '''
63}};
64
65def operands {{
66 #General Purpose Integer Reg Operands
67 'Rd': ('IntReg', 'uw', 'RD', 'IsInteger', 1, maybePCRead, maybePCWrite),
68 'Rm': ('IntReg', 'uw', 'RM', 'IsInteger', 2, maybePCRead, maybePCWrite),
69 'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3, maybePCRead, maybePCWrite),
70 'Rn': ('IntReg', 'uw', 'RN', 'IsInteger', 4, maybePCRead, maybePCWrite),
71 'R7': ('IntReg', 'uw', '7', 'IsInteger', 5),
72 'R0': ('IntReg', 'uw', '0', 'IsInteger', 0),
73
74 #Destination register for load/store double instructions
75 'Rdo': ('IntReg', 'uw', '(RD & ~1)', 'IsInteger', 4, maybePCRead, maybePCWrite),
76 'Rde': ('IntReg', 'uw', '(RD | 1)', 'IsInteger', 5, maybePCRead, maybePCWrite),
77
78 'Rhi': ('IntReg', 'uw', 'INTREG_RHI', 'IsInteger', 7),
79 'Rlo': ('IntReg', 'uw', 'INTREG_RLO', 'IsInteger', 8),
80 'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
|
71
72 #Register fields for microops
73 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
74 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
75
76 #General Purpose Floating Point Reg Operands
77 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
78 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
79 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
80
81 #Memory Operand
82 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
83
| 82
83 #Register fields for microops
84 'Ra' : ('IntReg', 'uw', 'ura', 'IsInteger', 11, maybePCRead, maybePCWrite),
85 'Rb' : ('IntReg', 'uw', 'urb', 'IsInteger', 12, maybePCRead, maybePCWrite),
86
87 #General Purpose Floating Point Reg Operands
88 'Fd': ('FloatReg', 'df', 'FD', 'IsFloating', 20),
89 'Fn': ('FloatReg', 'df', 'FN', 'IsFloating', 21),
90 'Fm': ('FloatReg', 'df', 'FM', 'IsFloating', 22),
91
92 #Memory Operand
93 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), 30),
94
|
84 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', (None, None, 'IsControl'), 40),
85 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', (None, None, 'IsControl'), 41),
86 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', (None, None, 'IsControl'), 42),
87 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', (None, None, 'IsControl'), 43),
88 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', (None, None, 'IsControl'), 44),
89 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', (None, None, 'IsControl'), 45),
| 95 'Cpsr': ('ControlReg', 'uw', 'MISCREG_CPSR', None, 40),
96 'Spsr': ('ControlReg', 'uw', 'MISCREG_SPSR', None, 41),
97 'Fpsr': ('ControlReg', 'uw', 'MISCREG_FPSR', None, 42),
98 'Fpsid': ('ControlReg', 'uw', 'MISCREG_FPSID', None, 43),
99 'Fpscr': ('ControlReg', 'uw', 'MISCREG_FPSCR', None, 44),
100 'Fpexc': ('ControlReg', 'uw', 'MISCREG_FPEXC', None, 45),
|