1// -*- mode:c++ -*-
2// Copyright (c) 2010-2014, 2016-2018 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Copyright (c) 2007-2008 The Florida State University
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16//
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18// modification, are permitted provided that the following conditions are
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21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
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26// this software without specific prior written permission.
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34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : 'int8_t',
44 'ub' : 'uint8_t',
45 'sh' : 'int16_t',
46 'uh' : 'uint16_t',
47 'sw' : 'int32_t',
48 'uw' : 'uint32_t',
49 'sd' : 'int64_t',
50 'ud' : 'uint64_t',
51 'tud' : 'std::array<uint64_t, 2>',
52 'sf' : 'float',
53 'df' : 'double',
54 'vc' : 'ArmISA::VecRegContainer',
55 # For operations that are implemented as a template
56 'x' : 'TPElem',
57 'xs' : 'TPSElem',
58 'xd' : 'TPDElem',
59 'pc' : 'ArmISA::VecPredRegContainer',
60 'pb' : 'uint8_t'
61}};
62
63let {{
64 maybePCRead = '''
65 ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
66 '''
67 maybeAlignedPCRead = '''
68 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
69 xc->%(func)s(this, %(op_idx)s))
70 '''
71 maybePCWrite = '''
72 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
73 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
74 '''
75 maybeIWPCWrite = '''
76 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
77 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
78 '''
79 maybeAIWPCWrite = '''
80 if (%(reg_idx)s == PCReg) {
81 bool thumb = THUMB;
82 if (thumb) {
83 setNextPC(xc, %(final_val)s);
84 } else {
85 setIWNextPC(xc, %(final_val)s);
86 }
87 } else {
88 xc->%(func)s(this, %(op_idx)s, %(final_val)s);
89 }
90 '''
91 aarch64Read = '''
92 ((xc->%(func)s(this, %(op_idx)s)) & mask(intWidth))
93 '''
94 aarch64Write = '''
95 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(intWidth))
96 '''
97 aarchX64Read = '''
98 ((xc->%(func)s(this, %(op_idx)s)) & mask(aarch64 ? 64 : 32))
99 '''
100 aarchX64Write = '''
101 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(aarch64 ? 64 : 32))
102 '''
103 aarchW64Read = '''
104 ((xc->%(func)s(this, %(op_idx)s)) & mask(32))
105 '''
106 aarchW64Write = '''
107 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
108 '''
109 cntrlNsBankedWrite = '''
110 xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()), %(final_val)s)
111 '''
112
113 cntrlNsBankedRead = '''
114 xc->readMiscReg(snsBankedIndex(op1, xc->tcBase()))
115 '''
116
117 #PCState operands need to have a sorting index (the number at the end)
118 #less than all the integer registers which might update the PC. That way
119 #if the flag bits of the pc state are updated and a branch happens through
120 #R15, the updates are layered properly and the R15 update isn't lost.
121 srtNormal = 5
122 srtCpsr = 4
123 srtBase = 3
124 srtPC = 2
125 srtMode = 1
126 srtEPC = 0
127
128 def vectorElem(idx, elem):
129 return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)
130
131 def vectorReg(idx, elems = None):
132 return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
133
134 def vectorRegElem(elem, ext = 'sf', zeroing = False):
135 return (elem, ext, zeroing)
136
137 def vecPredReg(idx):
138 return ('VecPredReg', 'pc', idx, None, srtNormal)
139
140 def intReg(idx):
141 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
142 maybePCRead, maybePCWrite)
143
144 def intReg64(idx):
145 return ('IntReg', 'ud', idx, 'IsInteger', srtNormal,
146 aarch64Read, aarch64Write)
147
148 def intRegX64(idx, id = srtNormal):
149 return ('IntReg', 'ud', idx, 'IsInteger', id,
150 aarchX64Read, aarchX64Write)
151
152 def intRegW64(idx, id = srtNormal):
153 return ('IntReg', 'ud', idx, 'IsInteger', id,
154 aarchW64Read, aarchW64Write)
155
156 def intRegNPC(idx):
157 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
158
159 def intRegAPC(idx, id = srtNormal):
160 return ('IntReg', 'uw', idx, 'IsInteger', id,
161 maybeAlignedPCRead, maybePCWrite)
162
163 def intRegIWPC(idx):
164 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
165 maybePCRead, maybeIWPCWrite)
166
167 def intRegAIWPC(idx):
168 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
169 maybePCRead, maybeAIWPCWrite)
170
171 def ccReg(idx):
172 return ('CCReg', 'uw', idx, None, srtNormal)
173
174 def cntrlReg(idx, id = srtNormal, type = 'uw'):
175 return ('ControlReg', type, idx, None, id)
176
177 def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'):
178 return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
179
180 def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'):
181 return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
182
183 def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
184 return ('ControlReg', type, idx, None, id)
185
186 def pcStateReg(idx, id):
187 return ('PCState', 'ud', idx, (None, None, 'IsControl'), id)
188}};
189
190def operands {{
191 #Abstracted integer reg operands
192 'Dest': intReg('dest'),
193 'Dest64': intReg64('dest'),
194 'XDest': intRegX64('dest'),
195 'WDest': intRegW64('dest'),
196 'IWDest': intRegIWPC('dest'),
197 'AIWDest': intRegAIWPC('dest'),
198 'Dest2': intReg('dest2'),
199 'XDest2': intRegX64('dest2'),
200 'IWDest2': intRegIWPC('dest2'),
201 'Result': intReg('result'),
202 'XResult': intRegX64('result'),
203 'XBase': intRegX64('base', id = srtBase),
204 'Base': intRegAPC('base', id = srtBase),
205 'XOffset': intRegX64('offset'),
206 'Index': intReg('index'),
207 'Shift': intReg('shift'),
208 'Op1': intReg('op1'),
209 'Op2': intReg('op2'),
210 'Op3': intReg('op3'),
211 'Op164': intReg64('op1'),
212 'Op264': intReg64('op2'),
213 'Op364': intReg64('op3'),
214 'XOp1': intRegX64('op1'),
215 'XOp2': intRegX64('op2'),
216 'XOp3': intRegX64('op3'),
217 'WOp1': intRegW64('op1'),
218 'WOp2': intRegW64('op2'),
219 'WOp3': intRegW64('op3'),
220 'Reg0': intReg('reg0'),
221 'Reg1': intReg('reg1'),
222 'Reg2': intReg('reg2'),
223 'Reg3': intReg('reg3'),
224
225 #Fixed index integer reg operands
226 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
227 'DecodedBankedIntReg': intRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
228 'LR': intRegNPC('INTREG_LR'),
229 'XLR': intRegX64('INTREG_X30'),
230 'R7': intRegNPC('7'),
231 # First four arguments are passed in registers
232 'R0': intRegNPC('0'),
233 'R1': intRegNPC('1'),
234 'R2': intRegNPC('2'),
235 'R3': intRegNPC('3'),
236 'X0': intRegX64('0'),
237 'X1': intRegX64('1'),
238 'X2': intRegX64('2'),
239 'X3': intRegX64('3'),
240
241 # Condition code registers
242 'CondCodesNZ': ccReg('CCREG_NZ'),
243 'CondCodesC': ccReg('CCREG_C'),
244 'CondCodesV': ccReg('CCREG_V'),
245 'CondCodesGE': ccReg('CCREG_GE'),
246 'OptCondCodesNZ': ccReg(
247 '''((condCode == COND_AL || condCode == COND_UC ||
248 condCode == COND_CC || condCode == COND_CS ||
249 condCode == COND_VS || condCode == COND_VC) ?
250 CCREG_ZERO : CCREG_NZ)'''),
251 'OptCondCodesC': ccReg(
252 '''((condCode == COND_HI || condCode == COND_LS ||
253 condCode == COND_CS || condCode == COND_CC) ?
254 CCREG_C : CCREG_ZERO)'''),
255 'OptShiftRmCondCodesC': ccReg(
256 '''((condCode == COND_HI || condCode == COND_LS ||
257 condCode == COND_CS || condCode == COND_CC ||
258 shiftType == ROR) ?
259 CCREG_C : CCREG_ZERO)'''),
260 'OptCondCodesV': ccReg(
261 '''((condCode == COND_VS || condCode == COND_VC ||
262 condCode == COND_GE || condCode == COND_LT ||
263 condCode == COND_GT || condCode == COND_LE) ?
264 CCREG_V : CCREG_ZERO)'''),
265 'FpCondCodes': ccReg('CCREG_FP'),
266
267 #Abstracted floating point reg operands
268 'FpDest': vectorElem('dest / 4', 'dest % 4'),
269 'FpDestP0': vectorElem('(dest + 0) / 4', '(dest + 0) % 4'),
270 'FpDestP1': vectorElem('(dest + 1) / 4', '(dest + 1) % 4'),
271 'FpDestP2': vectorElem('(dest + 2) / 4', '(dest + 2) % 4'),
272 'FpDestP3': vectorElem('(dest + 3) / 4', '(dest + 3) % 4'),
273 'FpDestP4': vectorElem('(dest + 4) / 4', '(dest + 4) % 4'),
274 'FpDestP5': vectorElem('(dest + 5) / 4', '(dest + 5) % 4'),
275 'FpDestP6': vectorElem('(dest + 6) / 4', '(dest + 6) % 4'),
276 'FpDestP7': vectorElem('(dest + 7) / 4', '(dest + 7) % 4'),
277
278 'FpDestS0P0': vectorElem(
279 '(dest + step * 0 + 0) / 4', '(dest + step * 0 + 0) % 4'),
280 'FpDestS0P1': vectorElem(
281 '(dest + step * 0 + 1) / 4', '(dest + step * 0 + 1) % 4'),
282 'FpDestS1P0': vectorElem(
283 '(dest + step * 1 + 0) / 4', '(dest + step * 1 + 0) % 4'),
284 'FpDestS1P1': vectorElem(
285 '(dest + step * 1 + 1) / 4', '(dest + step * 1 + 1) % 4'),
286 'FpDestS2P0': vectorElem(
287 '(dest + step * 2 + 0) / 4', '(dest + step * 2 + 0) % 4'),
288 'FpDestS2P1': vectorElem(
289 '(dest + step * 2 + 1) / 4', '(dest + step * 2 + 1) % 4'),
290 'FpDestS3P0': vectorElem(
291 '(dest + step * 3 + 0) / 4', '(dest + step * 3 + 0) % 4'),
292 'FpDestS3P1': vectorElem(
293 '(dest + step * 3 + 1) / 4', '(dest + step * 3 + 1) % 4'),
294
295 'FpDest2': vectorElem('dest2 / 4', 'dest2 % 4'),
296 'FpDest2P0': vectorElem('(dest2 + 0) / 4', '(dest2 + 0) % 4'),
297 'FpDest2P1': vectorElem('(dest2 + 1) / 4', '(dest2 + 1) % 4'),
298 'FpDest2P2': vectorElem('(dest2 + 2) / 4', '(dest2 + 2) % 4'),
299 'FpDest2P3': vectorElem('(dest2 + 3) / 4', '(dest2 + 3) % 4'),
300
301 'FpOp1': vectorElem('op1 / 4', 'op1 % 4'),
302 'FpOp1P0': vectorElem('(op1 + 0) / 4', '(op1 + 0) % 4'),
303 'FpOp1P1': vectorElem('(op1 + 1) / 4', '(op1 + 1) % 4'),
304 'FpOp1P2': vectorElem('(op1 + 2) / 4', '(op1 + 2) % 4'),
305 'FpOp1P3': vectorElem('(op1 + 3) / 4', '(op1 + 3) % 4'),
306 'FpOp1P4': vectorElem('(op1 + 4) / 4', '(op1 + 4) % 4'),
307 'FpOp1P5': vectorElem('(op1 + 5) / 4', '(op1 + 5) % 4'),
308 'FpOp1P6': vectorElem('(op1 + 6) / 4', '(op1 + 6) % 4'),
309 'FpOp1P7': vectorElem('(op1 + 7) / 4', '(op1 + 7) % 4'),
310
311 'FpOp1S0P0': vectorElem(
312 '(op1 + step * 0 + 0) / 4', '(op1 + step * 0 + 0) % 4'),
313 'FpOp1S0P1': vectorElem(
314 '(op1 + step * 0 + 1) / 4', '(op1 + step * 0 + 1) % 4'),
315 'FpOp1S1P0': vectorElem(
316 '(op1 + step * 1 + 0) / 4', '(op1 + step * 1 + 0) % 4'),
317 'FpOp1S1P1': vectorElem(
318 '(op1 + step * 1 + 1) / 4', '(op1 + step * 1 + 1) % 4'),
319 'FpOp1S2P0': vectorElem(
320 '(op1 + step * 2 + 0) / 4', '(op1 + step * 2 + 0) % 4'),
321 'FpOp1S2P1': vectorElem(
322 '(op1 + step * 2 + 1) / 4', '(op1 + step * 2 + 1) % 4'),
323 'FpOp1S3P0': vectorElem(
324 '(op1 + step * 3 + 0) / 4', '(op1 + step * 3 + 0) % 4'),
325 'FpOp1S3P1': vectorElem(
326 '(op1 + step * 3 + 1) / 4', '(op1 + step * 3 + 1) % 4'),
327
328 'FpOp2': vectorElem('op2 / 4', 'op2 % 4'),
329 'FpOp2P0': vectorElem('(op2 + 0) / 4', '(op2 + 0) % 4'),
330 'FpOp2P1': vectorElem('(op2 + 1) / 4', '(op2 + 1) % 4'),
331 'FpOp2P2': vectorElem('(op2 + 2) / 4', '(op2 + 2) % 4'),
332 'FpOp2P3': vectorElem('(op2 + 3) / 4', '(op2 + 3) % 4'),
333
334 # Create AArch64 unpacked view of the FP registers
335 # Name ::= 'AA64Vec' OpSpec [LaneSpec]
336 # OpSpec ::= IOSpec [Index] [Plus]
337 # IOSpec ::= 'S' | 'D'
338 # Index ::= '0' | ... | '9'
339 # Plus ::= [PlusAmount] ['l']
340 # PlusAmount ::= 'p' [PlusAmount]
341 # LaneSpec ::= 'L' Index
342 #
343 # All the constituents are hierarchically defined as part of the Vector
344 # Register they belong to
345
346 'AA64FpOp1': vectorReg('op1',
347 {
348 'AA64FpOp1P0': vectorRegElem('0'),
349 'AA64FpOp1P1': vectorRegElem('1'),
350 'AA64FpOp1P2': vectorRegElem('2'),
351 'AA64FpOp1P3': vectorRegElem('3'),
352 'AA64FpOp1S': vectorRegElem('0', 'sf', zeroing = True),
353 'AA64FpOp1D': vectorRegElem('0', 'df', zeroing = True),
354 'AA64FpOp1Q': vectorRegElem('0', 'tud', zeroing = True)
355 }),
356
357 'AA64FpOp2': vectorReg('op2',
358 {
359 'AA64FpOp2P0': vectorRegElem('0'),
360 'AA64FpOp2P1': vectorRegElem('1'),
361 'AA64FpOp2P2': vectorRegElem('2'),
362 'AA64FpOp2P3': vectorRegElem('3'),
363 'AA64FpOp2S': vectorRegElem('0', 'sf', zeroing = True),
364 'AA64FpOp2D': vectorRegElem('0', 'df', zeroing = True),
365 'AA64FpOp2Q': vectorRegElem('0', 'tud', zeroing = True)
366 }),
367
368 'AA64FpOp3': vectorReg('op3',
369 {
370 'AA64FpOp3P0': vectorRegElem('0'),
371 'AA64FpOp3P1': vectorRegElem('1'),
372 'AA64FpOp3P2': vectorRegElem('2'),
373 'AA64FpOp3P3': vectorRegElem('3'),
374 'AA64FpOp3S': vectorRegElem('0', 'sf', zeroing = True),
375 'AA64FpOp3D': vectorRegElem('0', 'df', zeroing = True),
376 'AA64FpOp3Q': vectorRegElem('0', 'tud', zeroing = True)
377 }),
378
379 'AA64FpDest': vectorReg('dest',
380 {
381 'AA64FpDestP0': vectorRegElem('0'),
382 'AA64FpDestP1': vectorRegElem('1'),
383 'AA64FpDestP2': vectorRegElem('2'),
384 'AA64FpDestP3': vectorRegElem('3'),
385 'AA64FpDestS': vectorRegElem('0', 'sf', zeroing = True),
386 'AA64FpDestD': vectorRegElem('0', 'df', zeroing = True),
387 'AA64FpDestQ': vectorRegElem('0', 'tud', zeroing = True)
388 }),
389
390 'AA64FpDest2': vectorReg('dest2',
391 {
392 'AA64FpDest2P0': vectorRegElem('0'),
393 'AA64FpDest2P1': vectorRegElem('1'),
394 'AA64FpDest2P2': vectorRegElem('2'),
395 'AA64FpDest2P3': vectorRegElem('3'),
396 'AA64FpDest2S': vectorRegElem('0', 'sf', zeroing = True),
397 'AA64FpDest2D': vectorRegElem('0', 'df', zeroing = True),
398 'AA64FpDest2Q': vectorRegElem('0', 'tud', zeroing = True)
399 }),
400
401 'AA64FpOp1V0': vectorReg('op1',
402 {
403 'AA64FpOp1P0V0': vectorRegElem('0'),
404 'AA64FpOp1P1V0': vectorRegElem('1'),
405 'AA64FpOp1P2V0': vectorRegElem('2'),
406 'AA64FpOp1P3V0': vectorRegElem('3'),
407 'AA64FpOp1SV0': vectorRegElem('0', 'sf', zeroing = True),
408 'AA64FpOp1DV0': vectorRegElem('0', 'df', zeroing = True),
409 'AA64FpOp1QV0': vectorRegElem('0', 'tud', zeroing = True)
410 }),
411
412 'AA64FpOp1V1': vectorReg('op1+1',
413 {
414 'AA64FpOp1P0V1': vectorRegElem('0'),
415 'AA64FpOp1P1V1': vectorRegElem('1'),
416 'AA64FpOp1P2V1': vectorRegElem('2'),
417 'AA64FpOp1P3V1': vectorRegElem('3'),
418 'AA64FpOp1SV1': vectorRegElem('0', 'sf', zeroing = True),
419 'AA64FpOp1DV1': vectorRegElem('0', 'df', zeroing = True),
420 'AA64FpOp1QV1': vectorRegElem('0', 'tud', zeroing = True)
421 }),
422
423 'AA64FpOp1V2': vectorReg('op1+2',
424 {
425 'AA64FpOp1P0V2': vectorRegElem('0'),
426 'AA64FpOp1P1V2': vectorRegElem('1'),
427 'AA64FpOp1P2V2': vectorRegElem('2'),
428 'AA64FpOp1P3V2': vectorRegElem('3'),
429 'AA64FpOp1SV2': vectorRegElem('0', 'sf', zeroing = True),
430 'AA64FpOp1DV2': vectorRegElem('0', 'df', zeroing = True),
431 'AA64FpOp1QV2': vectorRegElem('0', 'tud', zeroing = True)
432 }),
433
434 'AA64FpOp1V3': vectorReg('op1+3',
435 {
436 'AA64FpOp1P0V3': vectorRegElem('0'),
437 'AA64FpOp1P1V3': vectorRegElem('1'),
438 'AA64FpOp1P2V3': vectorRegElem('2'),
439 'AA64FpOp1P3V3': vectorRegElem('3'),
440 'AA64FpOp1SV3': vectorRegElem('0', 'sf', zeroing = True),
441 'AA64FpOp1DV3': vectorRegElem('0', 'df', zeroing = True),
442 'AA64FpOp1QV3': vectorRegElem('0', 'tud', zeroing = True)
443 }),
444
445 'AA64FpOp1V0S': vectorReg('(op1+0)%32',
446 {
447 'AA64FpOp1P0V0S': vectorRegElem('0'),
448 'AA64FpOp1P1V0S': vectorRegElem('1'),
449 'AA64FpOp1P2V0S': vectorRegElem('2'),
450 'AA64FpOp1P3V0S': vectorRegElem('3'),
451 'AA64FpOp1SV0S': vectorRegElem('0', 'sf', zeroing = True),
452 'AA64FpOp1DV0S': vectorRegElem('0', 'df', zeroing = True),
453 'AA64FpOp1QV0S': vectorRegElem('0', 'tud', zeroing = True)
454 }),
455
456 'AA64FpOp1V1S': vectorReg('(op1+1)%32',
457 {
458 'AA64FpOp1P0V1S': vectorRegElem('0'),
459 'AA64FpOp1P1V1S': vectorRegElem('1'),
460 'AA64FpOp1P2V1S': vectorRegElem('2'),
461 'AA64FpOp1P3V1S': vectorRegElem('3'),
462 'AA64FpOp1SV1S': vectorRegElem('0', 'sf', zeroing = True),
463 'AA64FpOp1DV1S': vectorRegElem('0', 'df', zeroing = True),
464 'AA64FpOp1QV1S': vectorRegElem('0', 'tud', zeroing = True)
465 }),
466
467 'AA64FpOp1V2S': vectorReg('(op1+2)%32',
468 {
469 'AA64FpOp1P0V2S': vectorRegElem('0'),
470 'AA64FpOp1P1V2S': vectorRegElem('1'),
471 'AA64FpOp1P2V2S': vectorRegElem('2'),
472 'AA64FpOp1P3V2S': vectorRegElem('3'),
473 'AA64FpOp1SV2S': vectorRegElem('0', 'sf', zeroing = True),
474 'AA64FpOp1DV2S': vectorRegElem('0', 'df', zeroing = True),
475 'AA64FpOp1QV2S': vectorRegElem('0', 'tud', zeroing = True)
476 }),
477
478 'AA64FpOp1V3S': vectorReg('(op1+3)%32',
479 {
480 'AA64FpOp1P0V3S': vectorRegElem('0'),
481 'AA64FpOp1P1V3S': vectorRegElem('1'),
482 'AA64FpOp1P2V3S': vectorRegElem('2'),
483 'AA64FpOp1P3V3S': vectorRegElem('3'),
484 'AA64FpOp1SV3S': vectorRegElem('0', 'sf', zeroing = True),
485 'AA64FpOp1DV3S': vectorRegElem('0', 'df', zeroing = True),
486 'AA64FpOp1QV3S': vectorRegElem('0', 'tud', zeroing = True)
487 }),
488
489 'AA64FpDestV0': vectorReg('(dest+0)',
490 {
491 'AA64FpDestP0V0': vectorRegElem('0'),
492 'AA64FpDestP1V0': vectorRegElem('1'),
493 'AA64FpDestP2V0': vectorRegElem('2'),
494 'AA64FpDestP3V0': vectorRegElem('3'),
495 'AA64FpDestSV0': vectorRegElem('0', 'sf', zeroing = True),
496 'AA64FpDestDV0': vectorRegElem('0', 'df', zeroing = True),
497 'AA64FpDestQV0': vectorRegElem('0', 'tud', zeroing = True)
498 }),
499
500 'AA64FpDestV1': vectorReg('(dest+1)',
501 {
502 'AA64FpDestP0V1': vectorRegElem('0'),
503 'AA64FpDestP1V1': vectorRegElem('1'),
504 'AA64FpDestP2V1': vectorRegElem('2'),
505 'AA64FpDestP3V1': vectorRegElem('3'),
506 'AA64FpDestSV1': vectorRegElem('0', 'sf', zeroing = True),
507 'AA64FpDestDV1': vectorRegElem('0', 'df', zeroing = True),
508 'AA64FpDestQV1': vectorRegElem('0', 'tud', zeroing = True)
509 }),
510
511 'AA64FpDestV0L': vectorReg('(dest+0)%32',
512 {
513 'AA64FpDestP0V0L': vectorRegElem('0'),
514 'AA64FpDestP1V0L': vectorRegElem('1'),
515 'AA64FpDestP2V0L': vectorRegElem('2'),
516 'AA64FpDestP3V0L': vectorRegElem('3'),
517 'AA64FpDestSV0L': vectorRegElem('0', 'sf', zeroing = True),
518 'AA64FpDestDV0L': vectorRegElem('0', 'df', zeroing = True),
519 'AA64FpDestQV0L': vectorRegElem('0', 'tud', zeroing = True)
520 }),
521
522 'AA64FpDestV1L': vectorReg('(dest+1)%32',
523 {
524 'AA64FpDestP0V1L': vectorRegElem('0'),
525 'AA64FpDestP1V1L': vectorRegElem('1'),
526 'AA64FpDestP2V1L': vectorRegElem('2'),
527 'AA64FpDestP3V1L': vectorRegElem('3'),
528 'AA64FpDestSV1L': vectorRegElem('0', 'sf', zeroing = True),
529 'AA64FpDestDV1L': vectorRegElem('0', 'df', zeroing = True),
530 'AA64FpDestQV1L': vectorRegElem('0', 'tud', zeroing = True)
531 }),
532
533 'AA64FpDestMerge': vectorReg('dest',
534 {
535 'AA64FpDestMergeP0': vectorRegElem('0'),
536 'AA64FpDestMergeP1': vectorRegElem('1'),
537 'AA64FpDestMergeP2': vectorRegElem('2'),
538 'AA64FpDestMergeP3': vectorRegElem('3'),
539 'AA64FpDestMergeS': vectorRegElem('0', 'sf', zeroing = True),
540 'AA64FpDestMergeD': vectorRegElem('0', 'df', zeroing = True),
541 'AA64FpDestMergeQ': vectorRegElem('0', 'tud', zeroing = True)
542 }),
543
544 'AA64FpBase': vectorReg('base',
545 {
546 'AA64FpBaseP0': vectorRegElem('0'),
547 'AA64FpBaseP1': vectorRegElem('1'),
548 'AA64FpBaseP2': vectorRegElem('2'),
549 'AA64FpBaseP3': vectorRegElem('3'),
550 'AA64FpBaseS': vectorRegElem('0', 'sf', zeroing = True),
551 'AA64FpBaseD': vectorRegElem('0', 'df', zeroing = True),
552 'AA64FpBaseQ': vectorRegElem('0', 'tud', zeroing = True)
553 }),
554
555 'AA64FpOffset': vectorReg('offset',
556 {
557 'AA64FpOffsetP0': vectorRegElem('0'),
558 'AA64FpOffsetP1': vectorRegElem('1'),
559 'AA64FpOffsetP2': vectorRegElem('2'),
560 'AA64FpOffsetP3': vectorRegElem('3'),
561 'AA64FpOffsetS': vectorRegElem('0', 'sf', zeroing = True),
562 'AA64FpOffsetD': vectorRegElem('0', 'df', zeroing = True),
563 'AA64FpOffsetQ': vectorRegElem('0', 'tud', zeroing = True)
564 }),
565
566 'AA64FpUreg0': vectorReg('VECREG_UREG0',
567 {
568 'AA64FpUreg0P0': vectorRegElem('0'),
569 'AA64FpUreg0P1': vectorRegElem('1'),
570 'AA64FpUreg0P2': vectorRegElem('2'),
571 'AA64FpUreg0P3': vectorRegElem('3'),
572 'AA64FpUreg0S': vectorRegElem('0', 'sf', zeroing = True),
573 'AA64FpUreg0D': vectorRegElem('0', 'df', zeroing = True),
574 'AA64FpUreg0Q': vectorRegElem('0', 'tud', zeroing = True)
575 }),
576
577 # Predicate register operands
578 'GpOp': vecPredReg('gp'),
579 'POp1': vecPredReg('op1'),
580 'POp2': vecPredReg('op2'),
581 'PDest': vecPredReg('dest'),
582 'PDestMerge': vecPredReg('dest'),
583 'Ffr': vecPredReg('PREDREG_FFR'),
| 1// -*- mode:c++ -*-
2// Copyright (c) 2010-2014, 2016-2018 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Copyright (c) 2007-2008 The Florida State University
15// All rights reserved.
16//
17// Redistribution and use in source and binary forms, with or without
18// modification, are permitted provided that the following conditions are
19// met: redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer;
21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
24// neither the name of the copyright holders nor the names of its
25// contributors may be used to endorse or promote products derived from
26// this software without specific prior written permission.
27//
28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : 'int8_t',
44 'ub' : 'uint8_t',
45 'sh' : 'int16_t',
46 'uh' : 'uint16_t',
47 'sw' : 'int32_t',
48 'uw' : 'uint32_t',
49 'sd' : 'int64_t',
50 'ud' : 'uint64_t',
51 'tud' : 'std::array<uint64_t, 2>',
52 'sf' : 'float',
53 'df' : 'double',
54 'vc' : 'ArmISA::VecRegContainer',
55 # For operations that are implemented as a template
56 'x' : 'TPElem',
57 'xs' : 'TPSElem',
58 'xd' : 'TPDElem',
59 'pc' : 'ArmISA::VecPredRegContainer',
60 'pb' : 'uint8_t'
61}};
62
63let {{
64 maybePCRead = '''
65 ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
66 '''
67 maybeAlignedPCRead = '''
68 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
69 xc->%(func)s(this, %(op_idx)s))
70 '''
71 maybePCWrite = '''
72 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
73 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
74 '''
75 maybeIWPCWrite = '''
76 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
77 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
78 '''
79 maybeAIWPCWrite = '''
80 if (%(reg_idx)s == PCReg) {
81 bool thumb = THUMB;
82 if (thumb) {
83 setNextPC(xc, %(final_val)s);
84 } else {
85 setIWNextPC(xc, %(final_val)s);
86 }
87 } else {
88 xc->%(func)s(this, %(op_idx)s, %(final_val)s);
89 }
90 '''
91 aarch64Read = '''
92 ((xc->%(func)s(this, %(op_idx)s)) & mask(intWidth))
93 '''
94 aarch64Write = '''
95 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(intWidth))
96 '''
97 aarchX64Read = '''
98 ((xc->%(func)s(this, %(op_idx)s)) & mask(aarch64 ? 64 : 32))
99 '''
100 aarchX64Write = '''
101 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(aarch64 ? 64 : 32))
102 '''
103 aarchW64Read = '''
104 ((xc->%(func)s(this, %(op_idx)s)) & mask(32))
105 '''
106 aarchW64Write = '''
107 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
108 '''
109 cntrlNsBankedWrite = '''
110 xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()), %(final_val)s)
111 '''
112
113 cntrlNsBankedRead = '''
114 xc->readMiscReg(snsBankedIndex(op1, xc->tcBase()))
115 '''
116
117 #PCState operands need to have a sorting index (the number at the end)
118 #less than all the integer registers which might update the PC. That way
119 #if the flag bits of the pc state are updated and a branch happens through
120 #R15, the updates are layered properly and the R15 update isn't lost.
121 srtNormal = 5
122 srtCpsr = 4
123 srtBase = 3
124 srtPC = 2
125 srtMode = 1
126 srtEPC = 0
127
128 def vectorElem(idx, elem):
129 return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)
130
131 def vectorReg(idx, elems = None):
132 return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
133
134 def vectorRegElem(elem, ext = 'sf', zeroing = False):
135 return (elem, ext, zeroing)
136
137 def vecPredReg(idx):
138 return ('VecPredReg', 'pc', idx, None, srtNormal)
139
140 def intReg(idx):
141 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
142 maybePCRead, maybePCWrite)
143
144 def intReg64(idx):
145 return ('IntReg', 'ud', idx, 'IsInteger', srtNormal,
146 aarch64Read, aarch64Write)
147
148 def intRegX64(idx, id = srtNormal):
149 return ('IntReg', 'ud', idx, 'IsInteger', id,
150 aarchX64Read, aarchX64Write)
151
152 def intRegW64(idx, id = srtNormal):
153 return ('IntReg', 'ud', idx, 'IsInteger', id,
154 aarchW64Read, aarchW64Write)
155
156 def intRegNPC(idx):
157 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
158
159 def intRegAPC(idx, id = srtNormal):
160 return ('IntReg', 'uw', idx, 'IsInteger', id,
161 maybeAlignedPCRead, maybePCWrite)
162
163 def intRegIWPC(idx):
164 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
165 maybePCRead, maybeIWPCWrite)
166
167 def intRegAIWPC(idx):
168 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
169 maybePCRead, maybeAIWPCWrite)
170
171 def ccReg(idx):
172 return ('CCReg', 'uw', idx, None, srtNormal)
173
174 def cntrlReg(idx, id = srtNormal, type = 'uw'):
175 return ('ControlReg', type, idx, None, id)
176
177 def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'):
178 return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
179
180 def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'):
181 return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
182
183 def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
184 return ('ControlReg', type, idx, None, id)
185
186 def pcStateReg(idx, id):
187 return ('PCState', 'ud', idx, (None, None, 'IsControl'), id)
188}};
189
190def operands {{
191 #Abstracted integer reg operands
192 'Dest': intReg('dest'),
193 'Dest64': intReg64('dest'),
194 'XDest': intRegX64('dest'),
195 'WDest': intRegW64('dest'),
196 'IWDest': intRegIWPC('dest'),
197 'AIWDest': intRegAIWPC('dest'),
198 'Dest2': intReg('dest2'),
199 'XDest2': intRegX64('dest2'),
200 'IWDest2': intRegIWPC('dest2'),
201 'Result': intReg('result'),
202 'XResult': intRegX64('result'),
203 'XBase': intRegX64('base', id = srtBase),
204 'Base': intRegAPC('base', id = srtBase),
205 'XOffset': intRegX64('offset'),
206 'Index': intReg('index'),
207 'Shift': intReg('shift'),
208 'Op1': intReg('op1'),
209 'Op2': intReg('op2'),
210 'Op3': intReg('op3'),
211 'Op164': intReg64('op1'),
212 'Op264': intReg64('op2'),
213 'Op364': intReg64('op3'),
214 'XOp1': intRegX64('op1'),
215 'XOp2': intRegX64('op2'),
216 'XOp3': intRegX64('op3'),
217 'WOp1': intRegW64('op1'),
218 'WOp2': intRegW64('op2'),
219 'WOp3': intRegW64('op3'),
220 'Reg0': intReg('reg0'),
221 'Reg1': intReg('reg1'),
222 'Reg2': intReg('reg2'),
223 'Reg3': intReg('reg3'),
224
225 #Fixed index integer reg operands
226 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
227 'DecodedBankedIntReg': intRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
228 'LR': intRegNPC('INTREG_LR'),
229 'XLR': intRegX64('INTREG_X30'),
230 'R7': intRegNPC('7'),
231 # First four arguments are passed in registers
232 'R0': intRegNPC('0'),
233 'R1': intRegNPC('1'),
234 'R2': intRegNPC('2'),
235 'R3': intRegNPC('3'),
236 'X0': intRegX64('0'),
237 'X1': intRegX64('1'),
238 'X2': intRegX64('2'),
239 'X3': intRegX64('3'),
240
241 # Condition code registers
242 'CondCodesNZ': ccReg('CCREG_NZ'),
243 'CondCodesC': ccReg('CCREG_C'),
244 'CondCodesV': ccReg('CCREG_V'),
245 'CondCodesGE': ccReg('CCREG_GE'),
246 'OptCondCodesNZ': ccReg(
247 '''((condCode == COND_AL || condCode == COND_UC ||
248 condCode == COND_CC || condCode == COND_CS ||
249 condCode == COND_VS || condCode == COND_VC) ?
250 CCREG_ZERO : CCREG_NZ)'''),
251 'OptCondCodesC': ccReg(
252 '''((condCode == COND_HI || condCode == COND_LS ||
253 condCode == COND_CS || condCode == COND_CC) ?
254 CCREG_C : CCREG_ZERO)'''),
255 'OptShiftRmCondCodesC': ccReg(
256 '''((condCode == COND_HI || condCode == COND_LS ||
257 condCode == COND_CS || condCode == COND_CC ||
258 shiftType == ROR) ?
259 CCREG_C : CCREG_ZERO)'''),
260 'OptCondCodesV': ccReg(
261 '''((condCode == COND_VS || condCode == COND_VC ||
262 condCode == COND_GE || condCode == COND_LT ||
263 condCode == COND_GT || condCode == COND_LE) ?
264 CCREG_V : CCREG_ZERO)'''),
265 'FpCondCodes': ccReg('CCREG_FP'),
266
267 #Abstracted floating point reg operands
268 'FpDest': vectorElem('dest / 4', 'dest % 4'),
269 'FpDestP0': vectorElem('(dest + 0) / 4', '(dest + 0) % 4'),
270 'FpDestP1': vectorElem('(dest + 1) / 4', '(dest + 1) % 4'),
271 'FpDestP2': vectorElem('(dest + 2) / 4', '(dest + 2) % 4'),
272 'FpDestP3': vectorElem('(dest + 3) / 4', '(dest + 3) % 4'),
273 'FpDestP4': vectorElem('(dest + 4) / 4', '(dest + 4) % 4'),
274 'FpDestP5': vectorElem('(dest + 5) / 4', '(dest + 5) % 4'),
275 'FpDestP6': vectorElem('(dest + 6) / 4', '(dest + 6) % 4'),
276 'FpDestP7': vectorElem('(dest + 7) / 4', '(dest + 7) % 4'),
277
278 'FpDestS0P0': vectorElem(
279 '(dest + step * 0 + 0) / 4', '(dest + step * 0 + 0) % 4'),
280 'FpDestS0P1': vectorElem(
281 '(dest + step * 0 + 1) / 4', '(dest + step * 0 + 1) % 4'),
282 'FpDestS1P0': vectorElem(
283 '(dest + step * 1 + 0) / 4', '(dest + step * 1 + 0) % 4'),
284 'FpDestS1P1': vectorElem(
285 '(dest + step * 1 + 1) / 4', '(dest + step * 1 + 1) % 4'),
286 'FpDestS2P0': vectorElem(
287 '(dest + step * 2 + 0) / 4', '(dest + step * 2 + 0) % 4'),
288 'FpDestS2P1': vectorElem(
289 '(dest + step * 2 + 1) / 4', '(dest + step * 2 + 1) % 4'),
290 'FpDestS3P0': vectorElem(
291 '(dest + step * 3 + 0) / 4', '(dest + step * 3 + 0) % 4'),
292 'FpDestS3P1': vectorElem(
293 '(dest + step * 3 + 1) / 4', '(dest + step * 3 + 1) % 4'),
294
295 'FpDest2': vectorElem('dest2 / 4', 'dest2 % 4'),
296 'FpDest2P0': vectorElem('(dest2 + 0) / 4', '(dest2 + 0) % 4'),
297 'FpDest2P1': vectorElem('(dest2 + 1) / 4', '(dest2 + 1) % 4'),
298 'FpDest2P2': vectorElem('(dest2 + 2) / 4', '(dest2 + 2) % 4'),
299 'FpDest2P3': vectorElem('(dest2 + 3) / 4', '(dest2 + 3) % 4'),
300
301 'FpOp1': vectorElem('op1 / 4', 'op1 % 4'),
302 'FpOp1P0': vectorElem('(op1 + 0) / 4', '(op1 + 0) % 4'),
303 'FpOp1P1': vectorElem('(op1 + 1) / 4', '(op1 + 1) % 4'),
304 'FpOp1P2': vectorElem('(op1 + 2) / 4', '(op1 + 2) % 4'),
305 'FpOp1P3': vectorElem('(op1 + 3) / 4', '(op1 + 3) % 4'),
306 'FpOp1P4': vectorElem('(op1 + 4) / 4', '(op1 + 4) % 4'),
307 'FpOp1P5': vectorElem('(op1 + 5) / 4', '(op1 + 5) % 4'),
308 'FpOp1P6': vectorElem('(op1 + 6) / 4', '(op1 + 6) % 4'),
309 'FpOp1P7': vectorElem('(op1 + 7) / 4', '(op1 + 7) % 4'),
310
311 'FpOp1S0P0': vectorElem(
312 '(op1 + step * 0 + 0) / 4', '(op1 + step * 0 + 0) % 4'),
313 'FpOp1S0P1': vectorElem(
314 '(op1 + step * 0 + 1) / 4', '(op1 + step * 0 + 1) % 4'),
315 'FpOp1S1P0': vectorElem(
316 '(op1 + step * 1 + 0) / 4', '(op1 + step * 1 + 0) % 4'),
317 'FpOp1S1P1': vectorElem(
318 '(op1 + step * 1 + 1) / 4', '(op1 + step * 1 + 1) % 4'),
319 'FpOp1S2P0': vectorElem(
320 '(op1 + step * 2 + 0) / 4', '(op1 + step * 2 + 0) % 4'),
321 'FpOp1S2P1': vectorElem(
322 '(op1 + step * 2 + 1) / 4', '(op1 + step * 2 + 1) % 4'),
323 'FpOp1S3P0': vectorElem(
324 '(op1 + step * 3 + 0) / 4', '(op1 + step * 3 + 0) % 4'),
325 'FpOp1S3P1': vectorElem(
326 '(op1 + step * 3 + 1) / 4', '(op1 + step * 3 + 1) % 4'),
327
328 'FpOp2': vectorElem('op2 / 4', 'op2 % 4'),
329 'FpOp2P0': vectorElem('(op2 + 0) / 4', '(op2 + 0) % 4'),
330 'FpOp2P1': vectorElem('(op2 + 1) / 4', '(op2 + 1) % 4'),
331 'FpOp2P2': vectorElem('(op2 + 2) / 4', '(op2 + 2) % 4'),
332 'FpOp2P3': vectorElem('(op2 + 3) / 4', '(op2 + 3) % 4'),
333
334 # Create AArch64 unpacked view of the FP registers
335 # Name ::= 'AA64Vec' OpSpec [LaneSpec]
336 # OpSpec ::= IOSpec [Index] [Plus]
337 # IOSpec ::= 'S' | 'D'
338 # Index ::= '0' | ... | '9'
339 # Plus ::= [PlusAmount] ['l']
340 # PlusAmount ::= 'p' [PlusAmount]
341 # LaneSpec ::= 'L' Index
342 #
343 # All the constituents are hierarchically defined as part of the Vector
344 # Register they belong to
345
346 'AA64FpOp1': vectorReg('op1',
347 {
348 'AA64FpOp1P0': vectorRegElem('0'),
349 'AA64FpOp1P1': vectorRegElem('1'),
350 'AA64FpOp1P2': vectorRegElem('2'),
351 'AA64FpOp1P3': vectorRegElem('3'),
352 'AA64FpOp1S': vectorRegElem('0', 'sf', zeroing = True),
353 'AA64FpOp1D': vectorRegElem('0', 'df', zeroing = True),
354 'AA64FpOp1Q': vectorRegElem('0', 'tud', zeroing = True)
355 }),
356
357 'AA64FpOp2': vectorReg('op2',
358 {
359 'AA64FpOp2P0': vectorRegElem('0'),
360 'AA64FpOp2P1': vectorRegElem('1'),
361 'AA64FpOp2P2': vectorRegElem('2'),
362 'AA64FpOp2P3': vectorRegElem('3'),
363 'AA64FpOp2S': vectorRegElem('0', 'sf', zeroing = True),
364 'AA64FpOp2D': vectorRegElem('0', 'df', zeroing = True),
365 'AA64FpOp2Q': vectorRegElem('0', 'tud', zeroing = True)
366 }),
367
368 'AA64FpOp3': vectorReg('op3',
369 {
370 'AA64FpOp3P0': vectorRegElem('0'),
371 'AA64FpOp3P1': vectorRegElem('1'),
372 'AA64FpOp3P2': vectorRegElem('2'),
373 'AA64FpOp3P3': vectorRegElem('3'),
374 'AA64FpOp3S': vectorRegElem('0', 'sf', zeroing = True),
375 'AA64FpOp3D': vectorRegElem('0', 'df', zeroing = True),
376 'AA64FpOp3Q': vectorRegElem('0', 'tud', zeroing = True)
377 }),
378
379 'AA64FpDest': vectorReg('dest',
380 {
381 'AA64FpDestP0': vectorRegElem('0'),
382 'AA64FpDestP1': vectorRegElem('1'),
383 'AA64FpDestP2': vectorRegElem('2'),
384 'AA64FpDestP3': vectorRegElem('3'),
385 'AA64FpDestS': vectorRegElem('0', 'sf', zeroing = True),
386 'AA64FpDestD': vectorRegElem('0', 'df', zeroing = True),
387 'AA64FpDestQ': vectorRegElem('0', 'tud', zeroing = True)
388 }),
389
390 'AA64FpDest2': vectorReg('dest2',
391 {
392 'AA64FpDest2P0': vectorRegElem('0'),
393 'AA64FpDest2P1': vectorRegElem('1'),
394 'AA64FpDest2P2': vectorRegElem('2'),
395 'AA64FpDest2P3': vectorRegElem('3'),
396 'AA64FpDest2S': vectorRegElem('0', 'sf', zeroing = True),
397 'AA64FpDest2D': vectorRegElem('0', 'df', zeroing = True),
398 'AA64FpDest2Q': vectorRegElem('0', 'tud', zeroing = True)
399 }),
400
401 'AA64FpOp1V0': vectorReg('op1',
402 {
403 'AA64FpOp1P0V0': vectorRegElem('0'),
404 'AA64FpOp1P1V0': vectorRegElem('1'),
405 'AA64FpOp1P2V0': vectorRegElem('2'),
406 'AA64FpOp1P3V0': vectorRegElem('3'),
407 'AA64FpOp1SV0': vectorRegElem('0', 'sf', zeroing = True),
408 'AA64FpOp1DV0': vectorRegElem('0', 'df', zeroing = True),
409 'AA64FpOp1QV0': vectorRegElem('0', 'tud', zeroing = True)
410 }),
411
412 'AA64FpOp1V1': vectorReg('op1+1',
413 {
414 'AA64FpOp1P0V1': vectorRegElem('0'),
415 'AA64FpOp1P1V1': vectorRegElem('1'),
416 'AA64FpOp1P2V1': vectorRegElem('2'),
417 'AA64FpOp1P3V1': vectorRegElem('3'),
418 'AA64FpOp1SV1': vectorRegElem('0', 'sf', zeroing = True),
419 'AA64FpOp1DV1': vectorRegElem('0', 'df', zeroing = True),
420 'AA64FpOp1QV1': vectorRegElem('0', 'tud', zeroing = True)
421 }),
422
423 'AA64FpOp1V2': vectorReg('op1+2',
424 {
425 'AA64FpOp1P0V2': vectorRegElem('0'),
426 'AA64FpOp1P1V2': vectorRegElem('1'),
427 'AA64FpOp1P2V2': vectorRegElem('2'),
428 'AA64FpOp1P3V2': vectorRegElem('3'),
429 'AA64FpOp1SV2': vectorRegElem('0', 'sf', zeroing = True),
430 'AA64FpOp1DV2': vectorRegElem('0', 'df', zeroing = True),
431 'AA64FpOp1QV2': vectorRegElem('0', 'tud', zeroing = True)
432 }),
433
434 'AA64FpOp1V3': vectorReg('op1+3',
435 {
436 'AA64FpOp1P0V3': vectorRegElem('0'),
437 'AA64FpOp1P1V3': vectorRegElem('1'),
438 'AA64FpOp1P2V3': vectorRegElem('2'),
439 'AA64FpOp1P3V3': vectorRegElem('3'),
440 'AA64FpOp1SV3': vectorRegElem('0', 'sf', zeroing = True),
441 'AA64FpOp1DV3': vectorRegElem('0', 'df', zeroing = True),
442 'AA64FpOp1QV3': vectorRegElem('0', 'tud', zeroing = True)
443 }),
444
445 'AA64FpOp1V0S': vectorReg('(op1+0)%32',
446 {
447 'AA64FpOp1P0V0S': vectorRegElem('0'),
448 'AA64FpOp1P1V0S': vectorRegElem('1'),
449 'AA64FpOp1P2V0S': vectorRegElem('2'),
450 'AA64FpOp1P3V0S': vectorRegElem('3'),
451 'AA64FpOp1SV0S': vectorRegElem('0', 'sf', zeroing = True),
452 'AA64FpOp1DV0S': vectorRegElem('0', 'df', zeroing = True),
453 'AA64FpOp1QV0S': vectorRegElem('0', 'tud', zeroing = True)
454 }),
455
456 'AA64FpOp1V1S': vectorReg('(op1+1)%32',
457 {
458 'AA64FpOp1P0V1S': vectorRegElem('0'),
459 'AA64FpOp1P1V1S': vectorRegElem('1'),
460 'AA64FpOp1P2V1S': vectorRegElem('2'),
461 'AA64FpOp1P3V1S': vectorRegElem('3'),
462 'AA64FpOp1SV1S': vectorRegElem('0', 'sf', zeroing = True),
463 'AA64FpOp1DV1S': vectorRegElem('0', 'df', zeroing = True),
464 'AA64FpOp1QV1S': vectorRegElem('0', 'tud', zeroing = True)
465 }),
466
467 'AA64FpOp1V2S': vectorReg('(op1+2)%32',
468 {
469 'AA64FpOp1P0V2S': vectorRegElem('0'),
470 'AA64FpOp1P1V2S': vectorRegElem('1'),
471 'AA64FpOp1P2V2S': vectorRegElem('2'),
472 'AA64FpOp1P3V2S': vectorRegElem('3'),
473 'AA64FpOp1SV2S': vectorRegElem('0', 'sf', zeroing = True),
474 'AA64FpOp1DV2S': vectorRegElem('0', 'df', zeroing = True),
475 'AA64FpOp1QV2S': vectorRegElem('0', 'tud', zeroing = True)
476 }),
477
478 'AA64FpOp1V3S': vectorReg('(op1+3)%32',
479 {
480 'AA64FpOp1P0V3S': vectorRegElem('0'),
481 'AA64FpOp1P1V3S': vectorRegElem('1'),
482 'AA64FpOp1P2V3S': vectorRegElem('2'),
483 'AA64FpOp1P3V3S': vectorRegElem('3'),
484 'AA64FpOp1SV3S': vectorRegElem('0', 'sf', zeroing = True),
485 'AA64FpOp1DV3S': vectorRegElem('0', 'df', zeroing = True),
486 'AA64FpOp1QV3S': vectorRegElem('0', 'tud', zeroing = True)
487 }),
488
489 'AA64FpDestV0': vectorReg('(dest+0)',
490 {
491 'AA64FpDestP0V0': vectorRegElem('0'),
492 'AA64FpDestP1V0': vectorRegElem('1'),
493 'AA64FpDestP2V0': vectorRegElem('2'),
494 'AA64FpDestP3V0': vectorRegElem('3'),
495 'AA64FpDestSV0': vectorRegElem('0', 'sf', zeroing = True),
496 'AA64FpDestDV0': vectorRegElem('0', 'df', zeroing = True),
497 'AA64FpDestQV0': vectorRegElem('0', 'tud', zeroing = True)
498 }),
499
500 'AA64FpDestV1': vectorReg('(dest+1)',
501 {
502 'AA64FpDestP0V1': vectorRegElem('0'),
503 'AA64FpDestP1V1': vectorRegElem('1'),
504 'AA64FpDestP2V1': vectorRegElem('2'),
505 'AA64FpDestP3V1': vectorRegElem('3'),
506 'AA64FpDestSV1': vectorRegElem('0', 'sf', zeroing = True),
507 'AA64FpDestDV1': vectorRegElem('0', 'df', zeroing = True),
508 'AA64FpDestQV1': vectorRegElem('0', 'tud', zeroing = True)
509 }),
510
511 'AA64FpDestV0L': vectorReg('(dest+0)%32',
512 {
513 'AA64FpDestP0V0L': vectorRegElem('0'),
514 'AA64FpDestP1V0L': vectorRegElem('1'),
515 'AA64FpDestP2V0L': vectorRegElem('2'),
516 'AA64FpDestP3V0L': vectorRegElem('3'),
517 'AA64FpDestSV0L': vectorRegElem('0', 'sf', zeroing = True),
518 'AA64FpDestDV0L': vectorRegElem('0', 'df', zeroing = True),
519 'AA64FpDestQV0L': vectorRegElem('0', 'tud', zeroing = True)
520 }),
521
522 'AA64FpDestV1L': vectorReg('(dest+1)%32',
523 {
524 'AA64FpDestP0V1L': vectorRegElem('0'),
525 'AA64FpDestP1V1L': vectorRegElem('1'),
526 'AA64FpDestP2V1L': vectorRegElem('2'),
527 'AA64FpDestP3V1L': vectorRegElem('3'),
528 'AA64FpDestSV1L': vectorRegElem('0', 'sf', zeroing = True),
529 'AA64FpDestDV1L': vectorRegElem('0', 'df', zeroing = True),
530 'AA64FpDestQV1L': vectorRegElem('0', 'tud', zeroing = True)
531 }),
532
533 'AA64FpDestMerge': vectorReg('dest',
534 {
535 'AA64FpDestMergeP0': vectorRegElem('0'),
536 'AA64FpDestMergeP1': vectorRegElem('1'),
537 'AA64FpDestMergeP2': vectorRegElem('2'),
538 'AA64FpDestMergeP3': vectorRegElem('3'),
539 'AA64FpDestMergeS': vectorRegElem('0', 'sf', zeroing = True),
540 'AA64FpDestMergeD': vectorRegElem('0', 'df', zeroing = True),
541 'AA64FpDestMergeQ': vectorRegElem('0', 'tud', zeroing = True)
542 }),
543
544 'AA64FpBase': vectorReg('base',
545 {
546 'AA64FpBaseP0': vectorRegElem('0'),
547 'AA64FpBaseP1': vectorRegElem('1'),
548 'AA64FpBaseP2': vectorRegElem('2'),
549 'AA64FpBaseP3': vectorRegElem('3'),
550 'AA64FpBaseS': vectorRegElem('0', 'sf', zeroing = True),
551 'AA64FpBaseD': vectorRegElem('0', 'df', zeroing = True),
552 'AA64FpBaseQ': vectorRegElem('0', 'tud', zeroing = True)
553 }),
554
555 'AA64FpOffset': vectorReg('offset',
556 {
557 'AA64FpOffsetP0': vectorRegElem('0'),
558 'AA64FpOffsetP1': vectorRegElem('1'),
559 'AA64FpOffsetP2': vectorRegElem('2'),
560 'AA64FpOffsetP3': vectorRegElem('3'),
561 'AA64FpOffsetS': vectorRegElem('0', 'sf', zeroing = True),
562 'AA64FpOffsetD': vectorRegElem('0', 'df', zeroing = True),
563 'AA64FpOffsetQ': vectorRegElem('0', 'tud', zeroing = True)
564 }),
565
566 'AA64FpUreg0': vectorReg('VECREG_UREG0',
567 {
568 'AA64FpUreg0P0': vectorRegElem('0'),
569 'AA64FpUreg0P1': vectorRegElem('1'),
570 'AA64FpUreg0P2': vectorRegElem('2'),
571 'AA64FpUreg0P3': vectorRegElem('3'),
572 'AA64FpUreg0S': vectorRegElem('0', 'sf', zeroing = True),
573 'AA64FpUreg0D': vectorRegElem('0', 'df', zeroing = True),
574 'AA64FpUreg0Q': vectorRegElem('0', 'tud', zeroing = True)
575 }),
576
577 # Predicate register operands
578 'GpOp': vecPredReg('gp'),
579 'POp1': vecPredReg('op1'),
580 'POp2': vecPredReg('op2'),
581 'PDest': vecPredReg('dest'),
582 'PDestMerge': vecPredReg('dest'),
583 'Ffr': vecPredReg('PREDREG_FFR'),
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