operands.isa (12134:604f47f63877) operands.isa (12386:2bf5fb25a5f1)
1// -*- mode:c++ -*-
2// Copyright (c) 2010-2014, 2016 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Copyright (c) 2007-2008 The Florida State University
15// All rights reserved.
16//
17// Redistribution and use in source and binary forms, with or without
18// modification, are permitted provided that the following conditions are
19// met: redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer;
21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
24// neither the name of the copyright holders nor the names of its
25// contributors may be used to endorse or promote products derived from
26// this software without specific prior written permission.
27//
28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : 'int8_t',
44 'ub' : 'uint8_t',
45 'sh' : 'int16_t',
46 'uh' : 'uint16_t',
47 'sw' : 'int32_t',
48 'uw' : 'uint32_t',
49 'ud' : 'uint64_t',
1// -*- mode:c++ -*-
2// Copyright (c) 2010-2014, 2016 ARM Limited
3// All rights reserved
4//
5// The license below extends only to copyright in the software and shall
6// not be construed as granting a license to any other intellectual
7// property including but not limited to intellectual property relating
8// to a hardware implementation of the functionality of the software
9// licensed hereunder. You may use the software subject to the license
10// terms below provided that you ensure that this notice is replicated
11// unmodified and in its entirety in all distributions of the software,
12// modified or unmodified, in source code or in binary form.
13//
14// Copyright (c) 2007-2008 The Florida State University
15// All rights reserved.
16//
17// Redistribution and use in source and binary forms, with or without
18// modification, are permitted provided that the following conditions are
19// met: redistributions of source code must retain the above copyright
20// notice, this list of conditions and the following disclaimer;
21// redistributions in binary form must reproduce the above copyright
22// notice, this list of conditions and the following disclaimer in the
23// documentation and/or other materials provided with the distribution;
24// neither the name of the copyright holders nor the names of its
25// contributors may be used to endorse or promote products derived from
26// this software without specific prior written permission.
27//
28// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39//
40// Authors: Stephen Hines
41
42def operand_types {{
43 'sb' : 'int8_t',
44 'ub' : 'uint8_t',
45 'sh' : 'int16_t',
46 'uh' : 'uint16_t',
47 'sw' : 'int32_t',
48 'uw' : 'uint32_t',
49 'ud' : 'uint64_t',
50 'tud' : 'Twin64_t',
50 'tud' : 'std::array<uint64_t, 2>',
51 'sf' : 'float',
52 'df' : 'double',
53 'vc' : 'TheISA::VecRegContainer',
54 # For operations that are implemented as a template
55 'x' : 'TPElem',
56}};
57
58let {{
59 maybePCRead = '''
60 ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
61 '''
62 maybeAlignedPCRead = '''
63 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
64 xc->%(func)s(this, %(op_idx)s))
65 '''
66 maybePCWrite = '''
67 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
68 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
69 '''
70 maybeIWPCWrite = '''
71 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
72 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
73 '''
74 maybeAIWPCWrite = '''
75 if (%(reg_idx)s == PCReg) {
76 bool thumb = THUMB;
77 if (thumb) {
78 setNextPC(xc, %(final_val)s);
79 } else {
80 setIWNextPC(xc, %(final_val)s);
81 }
82 } else {
83 xc->%(func)s(this, %(op_idx)s, %(final_val)s);
84 }
85 '''
86 aarch64Read = '''
87 ((xc->%(func)s(this, %(op_idx)s)) & mask(intWidth))
88 '''
89 aarch64Write = '''
90 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(intWidth))
91 '''
92 aarchX64Read = '''
93 ((xc->%(func)s(this, %(op_idx)s)) & mask(aarch64 ? 64 : 32))
94 '''
95 aarchX64Write = '''
96 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(aarch64 ? 64 : 32))
97 '''
98 aarchW64Read = '''
99 ((xc->%(func)s(this, %(op_idx)s)) & mask(32))
100 '''
101 aarchW64Write = '''
102 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
103 '''
104 cntrlNsBankedWrite = '''
105 xc->setMiscReg(flattenMiscRegNsBanked(dest, xc->tcBase()), %(final_val)s)
106 '''
107
108 cntrlNsBankedRead = '''
109 xc->readMiscReg(flattenMiscRegNsBanked(op1, xc->tcBase()))
110 '''
111
112 #PCState operands need to have a sorting index (the number at the end)
113 #less than all the integer registers which might update the PC. That way
114 #if the flag bits of the pc state are updated and a branch happens through
115 #R15, the updates are layered properly and the R15 update isn't lost.
116 srtNormal = 5
117 srtCpsr = 4
118 srtBase = 3
119 srtPC = 2
120 srtMode = 1
121 srtEPC = 0
122
123 def vectorElem(idx, elem):
124 return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)
125
126 def vectorReg(idx, elems = None):
127 return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
128
129 def vectorRegElem(elem, ext = 'sf', zeroing = False):
130 return (elem, ext, zeroing)
131
132 def floatReg(idx):
133 return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
134
135 def intReg(idx):
136 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
137 maybePCRead, maybePCWrite)
138
139 def intReg64(idx):
140 return ('IntReg', 'ud', idx, 'IsInteger', srtNormal,
141 aarch64Read, aarch64Write)
142
143 def intRegX64(idx, id = srtNormal):
144 return ('IntReg', 'ud', idx, 'IsInteger', id,
145 aarchX64Read, aarchX64Write)
146
147 def intRegW64(idx, id = srtNormal):
148 return ('IntReg', 'ud', idx, 'IsInteger', id,
149 aarchW64Read, aarchW64Write)
150
151 def intRegNPC(idx):
152 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
153
154 def intRegAPC(idx, id = srtNormal):
155 return ('IntReg', 'uw', idx, 'IsInteger', id,
156 maybeAlignedPCRead, maybePCWrite)
157
158 def intRegIWPC(idx):
159 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
160 maybePCRead, maybeIWPCWrite)
161
162 def intRegAIWPC(idx):
163 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
164 maybePCRead, maybeAIWPCWrite)
165
166 def ccReg(idx):
167 return ('CCReg', 'uw', idx, None, srtNormal)
168
169 def cntrlReg(idx, id = srtNormal, type = 'uw'):
170 return ('ControlReg', type, idx, None, id)
171
172 def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'):
173 return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
174
175 def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'):
176 return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
177
178 def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
179 return ('ControlReg', type, idx, None, id)
180
181 def pcStateReg(idx, id):
182 return ('PCState', 'ud', idx, (None, None, 'IsControl'), id)
183}};
184
185def operands {{
186 #Abstracted integer reg operands
187 'Dest': intReg('dest'),
188 'Dest64': intReg64('dest'),
189 'XDest': intRegX64('dest'),
190 'WDest': intRegW64('dest'),
191 'IWDest': intRegIWPC('dest'),
192 'AIWDest': intRegAIWPC('dest'),
193 'Dest2': intReg('dest2'),
194 'XDest2': intRegX64('dest2'),
195 'FDest2': floatReg('dest2'),
196 'IWDest2': intRegIWPC('dest2'),
197 'Result': intReg('result'),
198 'XResult': intRegX64('result'),
199 'XBase': intRegX64('base', id = srtBase),
200 'Base': intRegAPC('base', id = srtBase),
201 'XOffset': intRegX64('offset'),
202 'Index': intReg('index'),
203 'Shift': intReg('shift'),
204 'Op1': intReg('op1'),
205 'Op2': intReg('op2'),
206 'Op3': intReg('op3'),
207 'Op164': intReg64('op1'),
208 'Op264': intReg64('op2'),
209 'Op364': intReg64('op3'),
210 'XOp1': intRegX64('op1'),
211 'XOp2': intRegX64('op2'),
212 'XOp3': intRegX64('op3'),
213 'WOp1': intRegW64('op1'),
214 'WOp2': intRegW64('op2'),
215 'WOp3': intRegW64('op3'),
216 'Reg0': intReg('reg0'),
217 'Reg1': intReg('reg1'),
218 'Reg2': intReg('reg2'),
219 'Reg3': intReg('reg3'),
220
221 #Fixed index integer reg operands
222 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
223 'DecodedBankedIntReg': intRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
224 'LR': intRegNPC('INTREG_LR'),
225 'XLR': intRegX64('INTREG_X30'),
226 'R7': intRegNPC('7'),
227 # First four arguments are passed in registers
228 'R0': intRegNPC('0'),
229 'R1': intRegNPC('1'),
230 'R2': intRegNPC('2'),
231 'R3': intRegNPC('3'),
232 'X0': intRegX64('0'),
233 'X1': intRegX64('1'),
234 'X2': intRegX64('2'),
235 'X3': intRegX64('3'),
236
237 # Condition code registers
238 'CondCodesNZ': ccReg('CCREG_NZ'),
239 'CondCodesC': ccReg('CCREG_C'),
240 'CondCodesV': ccReg('CCREG_V'),
241 'CondCodesGE': ccReg('CCREG_GE'),
242 'OptCondCodesNZ': ccReg(
243 '''((condCode == COND_AL || condCode == COND_UC ||
244 condCode == COND_CC || condCode == COND_CS ||
245 condCode == COND_VS || condCode == COND_VC) ?
246 CCREG_ZERO : CCREG_NZ)'''),
247 'OptCondCodesC': ccReg(
248 '''((condCode == COND_HI || condCode == COND_LS ||
249 condCode == COND_CS || condCode == COND_CC) ?
250 CCREG_C : CCREG_ZERO)'''),
251 'OptShiftRmCondCodesC': ccReg(
252 '''((condCode == COND_HI || condCode == COND_LS ||
253 condCode == COND_CS || condCode == COND_CC ||
254 shiftType == ROR) ?
255 CCREG_C : CCREG_ZERO)'''),
256 'OptCondCodesV': ccReg(
257 '''((condCode == COND_VS || condCode == COND_VC ||
258 condCode == COND_GE || condCode == COND_LT ||
259 condCode == COND_GT || condCode == COND_LE) ?
260 CCREG_V : CCREG_ZERO)'''),
261 'FpCondCodes': ccReg('CCREG_FP'),
262
263 #Abstracted floating point reg operands
264 'FpDest': floatReg('(dest + 0)'),
265 'FpDestP0': floatReg('(dest + 0)'),
266 'FpDestP1': floatReg('(dest + 1)'),
267 'FpDestP2': floatReg('(dest + 2)'),
268 'FpDestP3': floatReg('(dest + 3)'),
269 'FpDestP4': floatReg('(dest + 4)'),
270 'FpDestP5': floatReg('(dest + 5)'),
271 'FpDestP6': floatReg('(dest + 6)'),
272 'FpDestP7': floatReg('(dest + 7)'),
273 'FpDestS0P0': floatReg('(dest + step * 0 + 0)'),
274 'FpDestS0P1': floatReg('(dest + step * 0 + 1)'),
275 'FpDestS1P0': floatReg('(dest + step * 1 + 0)'),
276 'FpDestS1P1': floatReg('(dest + step * 1 + 1)'),
277 'FpDestS2P0': floatReg('(dest + step * 2 + 0)'),
278 'FpDestS2P1': floatReg('(dest + step * 2 + 1)'),
279 'FpDestS3P0': floatReg('(dest + step * 3 + 0)'),
280 'FpDestS3P1': floatReg('(dest + step * 3 + 1)'),
281
282 'FpDest2': floatReg('(dest2 + 0)'),
283 'FpDest2P0': floatReg('(dest2 + 0)'),
284 'FpDest2P1': floatReg('(dest2 + 1)'),
285 'FpDest2P2': floatReg('(dest2 + 2)'),
286 'FpDest2P3': floatReg('(dest2 + 3)'),
287
288 'FpOp1': floatReg('(op1 + 0)'),
289 'FpOp1P0': floatReg('(op1 + 0)'),
290 'FpOp1P1': floatReg('(op1 + 1)'),
291 'FpOp1P2': floatReg('(op1 + 2)'),
292 'FpOp1P3': floatReg('(op1 + 3)'),
293 'FpOp1P4': floatReg('(op1 + 4)'),
294 'FpOp1P5': floatReg('(op1 + 5)'),
295 'FpOp1P6': floatReg('(op1 + 6)'),
296 'FpOp1P7': floatReg('(op1 + 7)'),
297 'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'),
298 'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'),
299 'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'),
300 'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'),
301 'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'),
302 'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'),
303 'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'),
304 'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),
305
306 'FpOp2': floatReg('(op2 + 0)'),
307 'FpOp2P0': floatReg('(op2 + 0)'),
308 'FpOp2P1': floatReg('(op2 + 1)'),
309 'FpOp2P2': floatReg('(op2 + 2)'),
310 'FpOp2P3': floatReg('(op2 + 3)'),
311
312 # Create AArch64 unpacked view of the FP registers
313 # Name ::= 'AA64Vec' OpSpec [LaneSpec]
314 # OpSpec ::= IOSpec [Index] [Plus]
315 # IOSpec ::= 'S' | 'D'
316 # Index ::= '0' | ... | '9'
317 # Plus ::= [PlusAmount] ['l']
318 # PlusAmount ::= 'p' [PlusAmount]
319 # LaneSpec ::= 'L' Index
320 #
321 # All the constituents are hierarchically defined as part of the Vector
322 # Register they belong to
323
324 'AA64FpOp1': vectorReg('op1',
325 {
326 'AA64FpOp1P0': vectorRegElem('0'),
327 'AA64FpOp1P1': vectorRegElem('1'),
328 'AA64FpOp1P2': vectorRegElem('2'),
329 'AA64FpOp1P3': vectorRegElem('3'),
330 'AA64FpOp1S': vectorRegElem('0', 'sf', zeroing = True),
331 'AA64FpOp1D': vectorRegElem('0', 'df', zeroing = True),
332 'AA64FpOp1Q': vectorRegElem('0', 'tud', zeroing = True)
333 }),
334
335 'AA64FpOp2': vectorReg('op2',
336 {
337 'AA64FpOp2P0': vectorRegElem('0'),
338 'AA64FpOp2P1': vectorRegElem('1'),
339 'AA64FpOp2P2': vectorRegElem('2'),
340 'AA64FpOp2P3': vectorRegElem('3'),
341 'AA64FpOp2S': vectorRegElem('0', 'sf', zeroing = True),
342 'AA64FpOp2D': vectorRegElem('0', 'df', zeroing = True),
343 'AA64FpOp2Q': vectorRegElem('0', 'tud', zeroing = True)
344 }),
345
346 'AA64FpOp3': vectorReg('op3',
347 {
348 'AA64FpOp3P0': vectorRegElem('0'),
349 'AA64FpOp3P1': vectorRegElem('1'),
350 'AA64FpOp3P2': vectorRegElem('2'),
351 'AA64FpOp3P3': vectorRegElem('3'),
352 'AA64FpOp3S': vectorRegElem('0', 'sf', zeroing = True),
353 'AA64FpOp3D': vectorRegElem('0', 'df', zeroing = True),
354 'AA64FpOp3Q': vectorRegElem('0', 'tud', zeroing = True)
355 }),
356
357 'AA64FpDest': vectorReg('dest',
358 {
359 'AA64FpDestP0': vectorRegElem('0'),
360 'AA64FpDestP1': vectorRegElem('1'),
361 'AA64FpDestP2': vectorRegElem('2'),
362 'AA64FpDestP3': vectorRegElem('3'),
363 'AA64FpDestS': vectorRegElem('0', 'sf', zeroing = True),
364 'AA64FpDestD': vectorRegElem('0', 'df', zeroing = True),
365 'AA64FpDestQ': vectorRegElem('0', 'tud', zeroing = True)
366 }),
367
368 'AA64FpDest2': vectorReg('dest2',
369 {
370 'AA64FpDest2P0': vectorRegElem('0'),
371 'AA64FpDest2P1': vectorRegElem('1'),
372 'AA64FpDest2P2': vectorRegElem('2'),
373 'AA64FpDest2P3': vectorRegElem('3'),
374 'AA64FpDest2S': vectorRegElem('0', 'sf', zeroing = True),
375 'AA64FpDest2D': vectorRegElem('0', 'df', zeroing = True),
376 'AA64FpDest2Q': vectorRegElem('0', 'tud', zeroing = True)
377 }),
378
379 'AA64FpOp1V0': vectorReg('op1',
380 {
381 'AA64FpOp1P0V0': vectorRegElem('0'),
382 'AA64FpOp1P1V0': vectorRegElem('1'),
383 'AA64FpOp1P2V0': vectorRegElem('2'),
384 'AA64FpOp1P3V0': vectorRegElem('3'),
385 'AA64FpOp1SV0': vectorRegElem('0', 'sf', zeroing = True),
386 'AA64FpOp1DV0': vectorRegElem('0', 'df', zeroing = True),
387 'AA64FpOp1QV0': vectorRegElem('0', 'tud', zeroing = True)
388 }),
389
390 'AA64FpOp1V1': vectorReg('op1+1',
391 {
392 'AA64FpOp1P0V1': vectorRegElem('0'),
393 'AA64FpOp1P1V1': vectorRegElem('1'),
394 'AA64FpOp1P2V1': vectorRegElem('2'),
395 'AA64FpOp1P3V1': vectorRegElem('3'),
396 'AA64FpOp1SV1': vectorRegElem('0', 'sf', zeroing = True),
397 'AA64FpOp1DV1': vectorRegElem('0', 'df', zeroing = True),
398 'AA64FpOp1QV1': vectorRegElem('0', 'tud', zeroing = True)
399 }),
400
401 'AA64FpOp1V2': vectorReg('op1+2',
402 {
403 'AA64FpOp1P0V2': vectorRegElem('0'),
404 'AA64FpOp1P1V2': vectorRegElem('1'),
405 'AA64FpOp1P2V2': vectorRegElem('2'),
406 'AA64FpOp1P3V2': vectorRegElem('3'),
407 'AA64FpOp1SV2': vectorRegElem('0', 'sf', zeroing = True),
408 'AA64FpOp1DV2': vectorRegElem('0', 'df', zeroing = True),
409 'AA64FpOp1QV2': vectorRegElem('0', 'tud', zeroing = True)
410 }),
411
412 'AA64FpOp1V3': vectorReg('op1+3',
413 {
414 'AA64FpOp1P0V3': vectorRegElem('0'),
415 'AA64FpOp1P1V3': vectorRegElem('1'),
416 'AA64FpOp1P2V3': vectorRegElem('2'),
417 'AA64FpOp1P3V3': vectorRegElem('3'),
418 'AA64FpOp1SV3': vectorRegElem('0', 'sf', zeroing = True),
419 'AA64FpOp1DV3': vectorRegElem('0', 'df', zeroing = True),
420 'AA64FpOp1QV3': vectorRegElem('0', 'tud', zeroing = True)
421 }),
422
423 'AA64FpOp1V0S': vectorReg('(op1+0)%32',
424 {
425 'AA64FpOp1P0V0S': vectorRegElem('0'),
426 'AA64FpOp1P1V0S': vectorRegElem('1'),
427 'AA64FpOp1P2V0S': vectorRegElem('2'),
428 'AA64FpOp1P3V0S': vectorRegElem('3'),
429 'AA64FpOp1SV0S': vectorRegElem('0', 'sf', zeroing = True),
430 'AA64FpOp1DV0S': vectorRegElem('0', 'df', zeroing = True),
431 'AA64FpOp1QV0S': vectorRegElem('0', 'tud', zeroing = True)
432 }),
433
434 'AA64FpOp1V1S': vectorReg('(op1+1)%32',
435 {
436 'AA64FpOp1P0V1S': vectorRegElem('0'),
437 'AA64FpOp1P1V1S': vectorRegElem('1'),
438 'AA64FpOp1P2V1S': vectorRegElem('2'),
439 'AA64FpOp1P3V1S': vectorRegElem('3'),
440 'AA64FpOp1SV1S': vectorRegElem('0', 'sf', zeroing = True),
441 'AA64FpOp1DV1S': vectorRegElem('0', 'df', zeroing = True),
442 'AA64FpOp1QV1S': vectorRegElem('0', 'tud', zeroing = True)
443 }),
444
445 'AA64FpOp1V2S': vectorReg('(op1+2)%32',
446 {
447 'AA64FpOp1P0V2S': vectorRegElem('0'),
448 'AA64FpOp1P1V2S': vectorRegElem('1'),
449 'AA64FpOp1P2V2S': vectorRegElem('2'),
450 'AA64FpOp1P3V2S': vectorRegElem('3'),
451 'AA64FpOp1SV2S': vectorRegElem('0', 'sf', zeroing = True),
452 'AA64FpOp1DV2S': vectorRegElem('0', 'df', zeroing = True),
453 'AA64FpOp1QV2S': vectorRegElem('0', 'tud', zeroing = True)
454 }),
455
456 'AA64FpOp1V3S': vectorReg('(op1+3)%32',
457 {
458 'AA64FpOp1P0V3S': vectorRegElem('0'),
459 'AA64FpOp1P1V3S': vectorRegElem('1'),
460 'AA64FpOp1P2V3S': vectorRegElem('2'),
461 'AA64FpOp1P3V3S': vectorRegElem('3'),
462 'AA64FpOp1SV3S': vectorRegElem('0', 'sf', zeroing = True),
463 'AA64FpOp1DV3S': vectorRegElem('0', 'df', zeroing = True),
464 'AA64FpOp1QV3S': vectorRegElem('0', 'tud', zeroing = True)
465 }),
466
467 'AA64FpDestV0': vectorReg('(dest+0)',
468 {
469 'AA64FpDestP0V0': vectorRegElem('0'),
470 'AA64FpDestP1V0': vectorRegElem('1'),
471 'AA64FpDestP2V0': vectorRegElem('2'),
472 'AA64FpDestP3V0': vectorRegElem('3'),
473 'AA64FpDestSV0': vectorRegElem('0', 'sf', zeroing = True),
474 'AA64FpDestDV0': vectorRegElem('0', 'df', zeroing = True),
475 'AA64FpDestQV0': vectorRegElem('0', 'tud', zeroing = True)
476 }),
477
478 'AA64FpDestV1': vectorReg('(dest+1)',
479 {
480 'AA64FpDestP0V1': vectorRegElem('0'),
481 'AA64FpDestP1V1': vectorRegElem('1'),
482 'AA64FpDestP2V1': vectorRegElem('2'),
483 'AA64FpDestP3V1': vectorRegElem('3'),
484 'AA64FpDestSV1': vectorRegElem('0', 'sf', zeroing = True),
485 'AA64FpDestDV1': vectorRegElem('0', 'df', zeroing = True),
486 'AA64FpDestQV1': vectorRegElem('0', 'tud', zeroing = True)
487 }),
488
489 'AA64FpDestV0L': vectorReg('(dest+0)%32',
490 {
491 'AA64FpDestP0V0L': vectorRegElem('0'),
492 'AA64FpDestP1V0L': vectorRegElem('1'),
493 'AA64FpDestP2V0L': vectorRegElem('2'),
494 'AA64FpDestP3V0L': vectorRegElem('3'),
495 'AA64FpDestSV0L': vectorRegElem('0', 'sf', zeroing = True),
496 'AA64FpDestDV0L': vectorRegElem('0', 'df', zeroing = True),
497 'AA64FpDestQV0L': vectorRegElem('0', 'tud', zeroing = True)
498 }),
499
500 'AA64FpDestV1L': vectorReg('(dest+1)%32',
501 {
502 'AA64FpDestP0V1L': vectorRegElem('0'),
503 'AA64FpDestP1V1L': vectorRegElem('1'),
504 'AA64FpDestP2V1L': vectorRegElem('2'),
505 'AA64FpDestP3V1L': vectorRegElem('3'),
506 'AA64FpDestSV1L': vectorRegElem('0', 'sf', zeroing = True),
507 'AA64FpDestDV1L': vectorRegElem('0', 'df', zeroing = True),
508 'AA64FpDestQV1L': vectorRegElem('0', 'tud', zeroing = True)
509 }),
510
511 #Abstracted control reg operands
512 'MiscDest': cntrlReg('dest'),
513 'MiscOp1': cntrlReg('op1'),
514 'MiscNsBankedDest': cntrlNsBankedReg('dest'),
515 'MiscNsBankedOp1': cntrlNsBankedReg('op1'),
516 'MiscNsBankedDest64': cntrlNsBankedReg64('dest'),
517 'MiscNsBankedOp164': cntrlNsBankedReg64('op1'),
518
519 #Fixed index control regs
520 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
521 'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr),
522 'Spsr': cntrlRegNC('MISCREG_SPSR'),
523 'Fpsr': cntrlRegNC('MISCREG_FPSR'),
524 'Fpsid': cntrlRegNC('MISCREG_FPSID'),
525 'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
526 'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
527 'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
528 'Cpacr': cntrlReg('MISCREG_CPACR'),
529 'Cpacr64': cntrlReg('MISCREG_CPACR_EL1'),
530 'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
531 'Nsacr': cntrlReg('MISCREG_NSACR'),
532 'ElrHyp': cntrlRegNC('MISCREG_ELR_HYP'),
533 'Hcr': cntrlReg('MISCREG_HCR'),
534 'Hcr64': cntrlReg('MISCREG_HCR_EL2'),
535 'Hdcr': cntrlReg('MISCREG_HDCR'),
536 'Hcptr': cntrlReg('MISCREG_HCPTR'),
537 'CptrEl264': cntrlReg('MISCREG_CPTR_EL2'),
538 'CptrEl364': cntrlReg('MISCREG_CPTR_EL3'),
539 'Hstr': cntrlReg('MISCREG_HSTR'),
540 'Scr': cntrlReg('MISCREG_SCR'),
541 'Scr64': cntrlReg('MISCREG_SCR_EL3'),
542 'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
543 'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
544 'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
545 'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'),
546
547 #Register fields for microops
548 'URa' : intReg('ura'),
549 'XURa' : intRegX64('ura'),
550 'WURa' : intRegW64('ura'),
551 'IWRa' : intRegIWPC('ura'),
552 'Fa' : floatReg('ura'),
553 'FaP1' : floatReg('ura + 1'),
554 'URb' : intReg('urb'),
555 'XURb' : intRegX64('urb'),
556 'URc' : intReg('urc'),
557 'XURc' : intRegX64('urc'),
558
559 #Memory Operand
560 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
561
562 #PCState fields
563 'RawPC': pcStateReg('pc', srtPC),
564 'PC': pcStateReg('instPC', srtPC),
565 'NPC': pcStateReg('instNPC', srtPC),
566 'pNPC': pcStateReg('instNPC', srtEPC),
567 'IWNPC': pcStateReg('instIWNPC', srtPC),
568 'Thumb': pcStateReg('thumb', srtPC),
569 'NextThumb': pcStateReg('nextThumb', srtMode),
570 'NextJazelle': pcStateReg('nextJazelle', srtMode),
571 'NextItState': pcStateReg('nextItstate', srtMode),
572 'Itstate': pcStateReg('itstate', srtMode),
573 'NextAArch64': pcStateReg('nextAArch64', srtMode),
574
575 #Register operands depending on a field in the instruction encoding. These
576 #should be avoided since they may not be portable across different
577 #encodings of the same instruction.
578 'Rd': intReg('RD'),
579 'Rm': intReg('RM'),
580 'Rs': intReg('RS'),
581 'Rn': intReg('RN'),
582 'Rt': intReg('RT')
583}};
51 'sf' : 'float',
52 'df' : 'double',
53 'vc' : 'TheISA::VecRegContainer',
54 # For operations that are implemented as a template
55 'x' : 'TPElem',
56}};
57
58let {{
59 maybePCRead = '''
60 ((%(reg_idx)s == PCReg) ? readPC(xc) : xc->%(func)s(this, %(op_idx)s))
61 '''
62 maybeAlignedPCRead = '''
63 ((%(reg_idx)s == PCReg) ? (roundDown(readPC(xc), 4)) :
64 xc->%(func)s(this, %(op_idx)s))
65 '''
66 maybePCWrite = '''
67 ((%(reg_idx)s == PCReg) ? setNextPC(xc, %(final_val)s) :
68 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
69 '''
70 maybeIWPCWrite = '''
71 ((%(reg_idx)s == PCReg) ? setIWNextPC(xc, %(final_val)s) :
72 xc->%(func)s(this, %(op_idx)s, %(final_val)s))
73 '''
74 maybeAIWPCWrite = '''
75 if (%(reg_idx)s == PCReg) {
76 bool thumb = THUMB;
77 if (thumb) {
78 setNextPC(xc, %(final_val)s);
79 } else {
80 setIWNextPC(xc, %(final_val)s);
81 }
82 } else {
83 xc->%(func)s(this, %(op_idx)s, %(final_val)s);
84 }
85 '''
86 aarch64Read = '''
87 ((xc->%(func)s(this, %(op_idx)s)) & mask(intWidth))
88 '''
89 aarch64Write = '''
90 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(intWidth))
91 '''
92 aarchX64Read = '''
93 ((xc->%(func)s(this, %(op_idx)s)) & mask(aarch64 ? 64 : 32))
94 '''
95 aarchX64Write = '''
96 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(aarch64 ? 64 : 32))
97 '''
98 aarchW64Read = '''
99 ((xc->%(func)s(this, %(op_idx)s)) & mask(32))
100 '''
101 aarchW64Write = '''
102 xc->%(func)s(this, %(op_idx)s, (%(final_val)s) & mask(32))
103 '''
104 cntrlNsBankedWrite = '''
105 xc->setMiscReg(flattenMiscRegNsBanked(dest, xc->tcBase()), %(final_val)s)
106 '''
107
108 cntrlNsBankedRead = '''
109 xc->readMiscReg(flattenMiscRegNsBanked(op1, xc->tcBase()))
110 '''
111
112 #PCState operands need to have a sorting index (the number at the end)
113 #less than all the integer registers which might update the PC. That way
114 #if the flag bits of the pc state are updated and a branch happens through
115 #R15, the updates are layered properly and the R15 update isn't lost.
116 srtNormal = 5
117 srtCpsr = 4
118 srtBase = 3
119 srtPC = 2
120 srtMode = 1
121 srtEPC = 0
122
123 def vectorElem(idx, elem):
124 return ('VecElem', 'sf', (idx, elem), 'IsVectorElem', srtNormal)
125
126 def vectorReg(idx, elems = None):
127 return ('VecReg', 'vc', (idx, elems) , 'IsVector', srtNormal)
128
129 def vectorRegElem(elem, ext = 'sf', zeroing = False):
130 return (elem, ext, zeroing)
131
132 def floatReg(idx):
133 return ('FloatReg', 'sf', idx, 'IsFloating', srtNormal)
134
135 def intReg(idx):
136 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
137 maybePCRead, maybePCWrite)
138
139 def intReg64(idx):
140 return ('IntReg', 'ud', idx, 'IsInteger', srtNormal,
141 aarch64Read, aarch64Write)
142
143 def intRegX64(idx, id = srtNormal):
144 return ('IntReg', 'ud', idx, 'IsInteger', id,
145 aarchX64Read, aarchX64Write)
146
147 def intRegW64(idx, id = srtNormal):
148 return ('IntReg', 'ud', idx, 'IsInteger', id,
149 aarchW64Read, aarchW64Write)
150
151 def intRegNPC(idx):
152 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
153
154 def intRegAPC(idx, id = srtNormal):
155 return ('IntReg', 'uw', idx, 'IsInteger', id,
156 maybeAlignedPCRead, maybePCWrite)
157
158 def intRegIWPC(idx):
159 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
160 maybePCRead, maybeIWPCWrite)
161
162 def intRegAIWPC(idx):
163 return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
164 maybePCRead, maybeAIWPCWrite)
165
166 def ccReg(idx):
167 return ('CCReg', 'uw', idx, None, srtNormal)
168
169 def cntrlReg(idx, id = srtNormal, type = 'uw'):
170 return ('ControlReg', type, idx, None, id)
171
172 def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'):
173 return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
174
175 def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'):
176 return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
177
178 def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
179 return ('ControlReg', type, idx, None, id)
180
181 def pcStateReg(idx, id):
182 return ('PCState', 'ud', idx, (None, None, 'IsControl'), id)
183}};
184
185def operands {{
186 #Abstracted integer reg operands
187 'Dest': intReg('dest'),
188 'Dest64': intReg64('dest'),
189 'XDest': intRegX64('dest'),
190 'WDest': intRegW64('dest'),
191 'IWDest': intRegIWPC('dest'),
192 'AIWDest': intRegAIWPC('dest'),
193 'Dest2': intReg('dest2'),
194 'XDest2': intRegX64('dest2'),
195 'FDest2': floatReg('dest2'),
196 'IWDest2': intRegIWPC('dest2'),
197 'Result': intReg('result'),
198 'XResult': intRegX64('result'),
199 'XBase': intRegX64('base', id = srtBase),
200 'Base': intRegAPC('base', id = srtBase),
201 'XOffset': intRegX64('offset'),
202 'Index': intReg('index'),
203 'Shift': intReg('shift'),
204 'Op1': intReg('op1'),
205 'Op2': intReg('op2'),
206 'Op3': intReg('op3'),
207 'Op164': intReg64('op1'),
208 'Op264': intReg64('op2'),
209 'Op364': intReg64('op3'),
210 'XOp1': intRegX64('op1'),
211 'XOp2': intRegX64('op2'),
212 'XOp3': intRegX64('op3'),
213 'WOp1': intRegW64('op1'),
214 'WOp2': intRegW64('op2'),
215 'WOp3': intRegW64('op3'),
216 'Reg0': intReg('reg0'),
217 'Reg1': intReg('reg1'),
218 'Reg2': intReg('reg2'),
219 'Reg3': intReg('reg3'),
220
221 #Fixed index integer reg operands
222 'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
223 'DecodedBankedIntReg': intRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
224 'LR': intRegNPC('INTREG_LR'),
225 'XLR': intRegX64('INTREG_X30'),
226 'R7': intRegNPC('7'),
227 # First four arguments are passed in registers
228 'R0': intRegNPC('0'),
229 'R1': intRegNPC('1'),
230 'R2': intRegNPC('2'),
231 'R3': intRegNPC('3'),
232 'X0': intRegX64('0'),
233 'X1': intRegX64('1'),
234 'X2': intRegX64('2'),
235 'X3': intRegX64('3'),
236
237 # Condition code registers
238 'CondCodesNZ': ccReg('CCREG_NZ'),
239 'CondCodesC': ccReg('CCREG_C'),
240 'CondCodesV': ccReg('CCREG_V'),
241 'CondCodesGE': ccReg('CCREG_GE'),
242 'OptCondCodesNZ': ccReg(
243 '''((condCode == COND_AL || condCode == COND_UC ||
244 condCode == COND_CC || condCode == COND_CS ||
245 condCode == COND_VS || condCode == COND_VC) ?
246 CCREG_ZERO : CCREG_NZ)'''),
247 'OptCondCodesC': ccReg(
248 '''((condCode == COND_HI || condCode == COND_LS ||
249 condCode == COND_CS || condCode == COND_CC) ?
250 CCREG_C : CCREG_ZERO)'''),
251 'OptShiftRmCondCodesC': ccReg(
252 '''((condCode == COND_HI || condCode == COND_LS ||
253 condCode == COND_CS || condCode == COND_CC ||
254 shiftType == ROR) ?
255 CCREG_C : CCREG_ZERO)'''),
256 'OptCondCodesV': ccReg(
257 '''((condCode == COND_VS || condCode == COND_VC ||
258 condCode == COND_GE || condCode == COND_LT ||
259 condCode == COND_GT || condCode == COND_LE) ?
260 CCREG_V : CCREG_ZERO)'''),
261 'FpCondCodes': ccReg('CCREG_FP'),
262
263 #Abstracted floating point reg operands
264 'FpDest': floatReg('(dest + 0)'),
265 'FpDestP0': floatReg('(dest + 0)'),
266 'FpDestP1': floatReg('(dest + 1)'),
267 'FpDestP2': floatReg('(dest + 2)'),
268 'FpDestP3': floatReg('(dest + 3)'),
269 'FpDestP4': floatReg('(dest + 4)'),
270 'FpDestP5': floatReg('(dest + 5)'),
271 'FpDestP6': floatReg('(dest + 6)'),
272 'FpDestP7': floatReg('(dest + 7)'),
273 'FpDestS0P0': floatReg('(dest + step * 0 + 0)'),
274 'FpDestS0P1': floatReg('(dest + step * 0 + 1)'),
275 'FpDestS1P0': floatReg('(dest + step * 1 + 0)'),
276 'FpDestS1P1': floatReg('(dest + step * 1 + 1)'),
277 'FpDestS2P0': floatReg('(dest + step * 2 + 0)'),
278 'FpDestS2P1': floatReg('(dest + step * 2 + 1)'),
279 'FpDestS3P0': floatReg('(dest + step * 3 + 0)'),
280 'FpDestS3P1': floatReg('(dest + step * 3 + 1)'),
281
282 'FpDest2': floatReg('(dest2 + 0)'),
283 'FpDest2P0': floatReg('(dest2 + 0)'),
284 'FpDest2P1': floatReg('(dest2 + 1)'),
285 'FpDest2P2': floatReg('(dest2 + 2)'),
286 'FpDest2P3': floatReg('(dest2 + 3)'),
287
288 'FpOp1': floatReg('(op1 + 0)'),
289 'FpOp1P0': floatReg('(op1 + 0)'),
290 'FpOp1P1': floatReg('(op1 + 1)'),
291 'FpOp1P2': floatReg('(op1 + 2)'),
292 'FpOp1P3': floatReg('(op1 + 3)'),
293 'FpOp1P4': floatReg('(op1 + 4)'),
294 'FpOp1P5': floatReg('(op1 + 5)'),
295 'FpOp1P6': floatReg('(op1 + 6)'),
296 'FpOp1P7': floatReg('(op1 + 7)'),
297 'FpOp1S0P0': floatReg('(op1 + step * 0 + 0)'),
298 'FpOp1S0P1': floatReg('(op1 + step * 0 + 1)'),
299 'FpOp1S1P0': floatReg('(op1 + step * 1 + 0)'),
300 'FpOp1S1P1': floatReg('(op1 + step * 1 + 1)'),
301 'FpOp1S2P0': floatReg('(op1 + step * 2 + 0)'),
302 'FpOp1S2P1': floatReg('(op1 + step * 2 + 1)'),
303 'FpOp1S3P0': floatReg('(op1 + step * 3 + 0)'),
304 'FpOp1S3P1': floatReg('(op1 + step * 3 + 1)'),
305
306 'FpOp2': floatReg('(op2 + 0)'),
307 'FpOp2P0': floatReg('(op2 + 0)'),
308 'FpOp2P1': floatReg('(op2 + 1)'),
309 'FpOp2P2': floatReg('(op2 + 2)'),
310 'FpOp2P3': floatReg('(op2 + 3)'),
311
312 # Create AArch64 unpacked view of the FP registers
313 # Name ::= 'AA64Vec' OpSpec [LaneSpec]
314 # OpSpec ::= IOSpec [Index] [Plus]
315 # IOSpec ::= 'S' | 'D'
316 # Index ::= '0' | ... | '9'
317 # Plus ::= [PlusAmount] ['l']
318 # PlusAmount ::= 'p' [PlusAmount]
319 # LaneSpec ::= 'L' Index
320 #
321 # All the constituents are hierarchically defined as part of the Vector
322 # Register they belong to
323
324 'AA64FpOp1': vectorReg('op1',
325 {
326 'AA64FpOp1P0': vectorRegElem('0'),
327 'AA64FpOp1P1': vectorRegElem('1'),
328 'AA64FpOp1P2': vectorRegElem('2'),
329 'AA64FpOp1P3': vectorRegElem('3'),
330 'AA64FpOp1S': vectorRegElem('0', 'sf', zeroing = True),
331 'AA64FpOp1D': vectorRegElem('0', 'df', zeroing = True),
332 'AA64FpOp1Q': vectorRegElem('0', 'tud', zeroing = True)
333 }),
334
335 'AA64FpOp2': vectorReg('op2',
336 {
337 'AA64FpOp2P0': vectorRegElem('0'),
338 'AA64FpOp2P1': vectorRegElem('1'),
339 'AA64FpOp2P2': vectorRegElem('2'),
340 'AA64FpOp2P3': vectorRegElem('3'),
341 'AA64FpOp2S': vectorRegElem('0', 'sf', zeroing = True),
342 'AA64FpOp2D': vectorRegElem('0', 'df', zeroing = True),
343 'AA64FpOp2Q': vectorRegElem('0', 'tud', zeroing = True)
344 }),
345
346 'AA64FpOp3': vectorReg('op3',
347 {
348 'AA64FpOp3P0': vectorRegElem('0'),
349 'AA64FpOp3P1': vectorRegElem('1'),
350 'AA64FpOp3P2': vectorRegElem('2'),
351 'AA64FpOp3P3': vectorRegElem('3'),
352 'AA64FpOp3S': vectorRegElem('0', 'sf', zeroing = True),
353 'AA64FpOp3D': vectorRegElem('0', 'df', zeroing = True),
354 'AA64FpOp3Q': vectorRegElem('0', 'tud', zeroing = True)
355 }),
356
357 'AA64FpDest': vectorReg('dest',
358 {
359 'AA64FpDestP0': vectorRegElem('0'),
360 'AA64FpDestP1': vectorRegElem('1'),
361 'AA64FpDestP2': vectorRegElem('2'),
362 'AA64FpDestP3': vectorRegElem('3'),
363 'AA64FpDestS': vectorRegElem('0', 'sf', zeroing = True),
364 'AA64FpDestD': vectorRegElem('0', 'df', zeroing = True),
365 'AA64FpDestQ': vectorRegElem('0', 'tud', zeroing = True)
366 }),
367
368 'AA64FpDest2': vectorReg('dest2',
369 {
370 'AA64FpDest2P0': vectorRegElem('0'),
371 'AA64FpDest2P1': vectorRegElem('1'),
372 'AA64FpDest2P2': vectorRegElem('2'),
373 'AA64FpDest2P3': vectorRegElem('3'),
374 'AA64FpDest2S': vectorRegElem('0', 'sf', zeroing = True),
375 'AA64FpDest2D': vectorRegElem('0', 'df', zeroing = True),
376 'AA64FpDest2Q': vectorRegElem('0', 'tud', zeroing = True)
377 }),
378
379 'AA64FpOp1V0': vectorReg('op1',
380 {
381 'AA64FpOp1P0V0': vectorRegElem('0'),
382 'AA64FpOp1P1V0': vectorRegElem('1'),
383 'AA64FpOp1P2V0': vectorRegElem('2'),
384 'AA64FpOp1P3V0': vectorRegElem('3'),
385 'AA64FpOp1SV0': vectorRegElem('0', 'sf', zeroing = True),
386 'AA64FpOp1DV0': vectorRegElem('0', 'df', zeroing = True),
387 'AA64FpOp1QV0': vectorRegElem('0', 'tud', zeroing = True)
388 }),
389
390 'AA64FpOp1V1': vectorReg('op1+1',
391 {
392 'AA64FpOp1P0V1': vectorRegElem('0'),
393 'AA64FpOp1P1V1': vectorRegElem('1'),
394 'AA64FpOp1P2V1': vectorRegElem('2'),
395 'AA64FpOp1P3V1': vectorRegElem('3'),
396 'AA64FpOp1SV1': vectorRegElem('0', 'sf', zeroing = True),
397 'AA64FpOp1DV1': vectorRegElem('0', 'df', zeroing = True),
398 'AA64FpOp1QV1': vectorRegElem('0', 'tud', zeroing = True)
399 }),
400
401 'AA64FpOp1V2': vectorReg('op1+2',
402 {
403 'AA64FpOp1P0V2': vectorRegElem('0'),
404 'AA64FpOp1P1V2': vectorRegElem('1'),
405 'AA64FpOp1P2V2': vectorRegElem('2'),
406 'AA64FpOp1P3V2': vectorRegElem('3'),
407 'AA64FpOp1SV2': vectorRegElem('0', 'sf', zeroing = True),
408 'AA64FpOp1DV2': vectorRegElem('0', 'df', zeroing = True),
409 'AA64FpOp1QV2': vectorRegElem('0', 'tud', zeroing = True)
410 }),
411
412 'AA64FpOp1V3': vectorReg('op1+3',
413 {
414 'AA64FpOp1P0V3': vectorRegElem('0'),
415 'AA64FpOp1P1V3': vectorRegElem('1'),
416 'AA64FpOp1P2V3': vectorRegElem('2'),
417 'AA64FpOp1P3V3': vectorRegElem('3'),
418 'AA64FpOp1SV3': vectorRegElem('0', 'sf', zeroing = True),
419 'AA64FpOp1DV3': vectorRegElem('0', 'df', zeroing = True),
420 'AA64FpOp1QV3': vectorRegElem('0', 'tud', zeroing = True)
421 }),
422
423 'AA64FpOp1V0S': vectorReg('(op1+0)%32',
424 {
425 'AA64FpOp1P0V0S': vectorRegElem('0'),
426 'AA64FpOp1P1V0S': vectorRegElem('1'),
427 'AA64FpOp1P2V0S': vectorRegElem('2'),
428 'AA64FpOp1P3V0S': vectorRegElem('3'),
429 'AA64FpOp1SV0S': vectorRegElem('0', 'sf', zeroing = True),
430 'AA64FpOp1DV0S': vectorRegElem('0', 'df', zeroing = True),
431 'AA64FpOp1QV0S': vectorRegElem('0', 'tud', zeroing = True)
432 }),
433
434 'AA64FpOp1V1S': vectorReg('(op1+1)%32',
435 {
436 'AA64FpOp1P0V1S': vectorRegElem('0'),
437 'AA64FpOp1P1V1S': vectorRegElem('1'),
438 'AA64FpOp1P2V1S': vectorRegElem('2'),
439 'AA64FpOp1P3V1S': vectorRegElem('3'),
440 'AA64FpOp1SV1S': vectorRegElem('0', 'sf', zeroing = True),
441 'AA64FpOp1DV1S': vectorRegElem('0', 'df', zeroing = True),
442 'AA64FpOp1QV1S': vectorRegElem('0', 'tud', zeroing = True)
443 }),
444
445 'AA64FpOp1V2S': vectorReg('(op1+2)%32',
446 {
447 'AA64FpOp1P0V2S': vectorRegElem('0'),
448 'AA64FpOp1P1V2S': vectorRegElem('1'),
449 'AA64FpOp1P2V2S': vectorRegElem('2'),
450 'AA64FpOp1P3V2S': vectorRegElem('3'),
451 'AA64FpOp1SV2S': vectorRegElem('0', 'sf', zeroing = True),
452 'AA64FpOp1DV2S': vectorRegElem('0', 'df', zeroing = True),
453 'AA64FpOp1QV2S': vectorRegElem('0', 'tud', zeroing = True)
454 }),
455
456 'AA64FpOp1V3S': vectorReg('(op1+3)%32',
457 {
458 'AA64FpOp1P0V3S': vectorRegElem('0'),
459 'AA64FpOp1P1V3S': vectorRegElem('1'),
460 'AA64FpOp1P2V3S': vectorRegElem('2'),
461 'AA64FpOp1P3V3S': vectorRegElem('3'),
462 'AA64FpOp1SV3S': vectorRegElem('0', 'sf', zeroing = True),
463 'AA64FpOp1DV3S': vectorRegElem('0', 'df', zeroing = True),
464 'AA64FpOp1QV3S': vectorRegElem('0', 'tud', zeroing = True)
465 }),
466
467 'AA64FpDestV0': vectorReg('(dest+0)',
468 {
469 'AA64FpDestP0V0': vectorRegElem('0'),
470 'AA64FpDestP1V0': vectorRegElem('1'),
471 'AA64FpDestP2V0': vectorRegElem('2'),
472 'AA64FpDestP3V0': vectorRegElem('3'),
473 'AA64FpDestSV0': vectorRegElem('0', 'sf', zeroing = True),
474 'AA64FpDestDV0': vectorRegElem('0', 'df', zeroing = True),
475 'AA64FpDestQV0': vectorRegElem('0', 'tud', zeroing = True)
476 }),
477
478 'AA64FpDestV1': vectorReg('(dest+1)',
479 {
480 'AA64FpDestP0V1': vectorRegElem('0'),
481 'AA64FpDestP1V1': vectorRegElem('1'),
482 'AA64FpDestP2V1': vectorRegElem('2'),
483 'AA64FpDestP3V1': vectorRegElem('3'),
484 'AA64FpDestSV1': vectorRegElem('0', 'sf', zeroing = True),
485 'AA64FpDestDV1': vectorRegElem('0', 'df', zeroing = True),
486 'AA64FpDestQV1': vectorRegElem('0', 'tud', zeroing = True)
487 }),
488
489 'AA64FpDestV0L': vectorReg('(dest+0)%32',
490 {
491 'AA64FpDestP0V0L': vectorRegElem('0'),
492 'AA64FpDestP1V0L': vectorRegElem('1'),
493 'AA64FpDestP2V0L': vectorRegElem('2'),
494 'AA64FpDestP3V0L': vectorRegElem('3'),
495 'AA64FpDestSV0L': vectorRegElem('0', 'sf', zeroing = True),
496 'AA64FpDestDV0L': vectorRegElem('0', 'df', zeroing = True),
497 'AA64FpDestQV0L': vectorRegElem('0', 'tud', zeroing = True)
498 }),
499
500 'AA64FpDestV1L': vectorReg('(dest+1)%32',
501 {
502 'AA64FpDestP0V1L': vectorRegElem('0'),
503 'AA64FpDestP1V1L': vectorRegElem('1'),
504 'AA64FpDestP2V1L': vectorRegElem('2'),
505 'AA64FpDestP3V1L': vectorRegElem('3'),
506 'AA64FpDestSV1L': vectorRegElem('0', 'sf', zeroing = True),
507 'AA64FpDestDV1L': vectorRegElem('0', 'df', zeroing = True),
508 'AA64FpDestQV1L': vectorRegElem('0', 'tud', zeroing = True)
509 }),
510
511 #Abstracted control reg operands
512 'MiscDest': cntrlReg('dest'),
513 'MiscOp1': cntrlReg('op1'),
514 'MiscNsBankedDest': cntrlNsBankedReg('dest'),
515 'MiscNsBankedOp1': cntrlNsBankedReg('op1'),
516 'MiscNsBankedDest64': cntrlNsBankedReg64('dest'),
517 'MiscNsBankedOp164': cntrlNsBankedReg64('op1'),
518
519 #Fixed index control regs
520 'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
521 'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr),
522 'Spsr': cntrlRegNC('MISCREG_SPSR'),
523 'Fpsr': cntrlRegNC('MISCREG_FPSR'),
524 'Fpsid': cntrlRegNC('MISCREG_FPSID'),
525 'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
526 'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
527 'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
528 'Cpacr': cntrlReg('MISCREG_CPACR'),
529 'Cpacr64': cntrlReg('MISCREG_CPACR_EL1'),
530 'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
531 'Nsacr': cntrlReg('MISCREG_NSACR'),
532 'ElrHyp': cntrlRegNC('MISCREG_ELR_HYP'),
533 'Hcr': cntrlReg('MISCREG_HCR'),
534 'Hcr64': cntrlReg('MISCREG_HCR_EL2'),
535 'Hdcr': cntrlReg('MISCREG_HDCR'),
536 'Hcptr': cntrlReg('MISCREG_HCPTR'),
537 'CptrEl264': cntrlReg('MISCREG_CPTR_EL2'),
538 'CptrEl364': cntrlReg('MISCREG_CPTR_EL3'),
539 'Hstr': cntrlReg('MISCREG_HSTR'),
540 'Scr': cntrlReg('MISCREG_SCR'),
541 'Scr64': cntrlReg('MISCREG_SCR_EL3'),
542 'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
543 'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
544 'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
545 'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'),
546
547 #Register fields for microops
548 'URa' : intReg('ura'),
549 'XURa' : intRegX64('ura'),
550 'WURa' : intRegW64('ura'),
551 'IWRa' : intRegIWPC('ura'),
552 'Fa' : floatReg('ura'),
553 'FaP1' : floatReg('ura + 1'),
554 'URb' : intReg('urb'),
555 'XURb' : intRegX64('urb'),
556 'URc' : intReg('urc'),
557 'XURc' : intRegX64('urc'),
558
559 #Memory Operand
560 'Mem': ('Mem', 'uw', None, ('IsMemRef', 'IsLoad', 'IsStore'), srtNormal),
561
562 #PCState fields
563 'RawPC': pcStateReg('pc', srtPC),
564 'PC': pcStateReg('instPC', srtPC),
565 'NPC': pcStateReg('instNPC', srtPC),
566 'pNPC': pcStateReg('instNPC', srtEPC),
567 'IWNPC': pcStateReg('instIWNPC', srtPC),
568 'Thumb': pcStateReg('thumb', srtPC),
569 'NextThumb': pcStateReg('nextThumb', srtMode),
570 'NextJazelle': pcStateReg('nextJazelle', srtMode),
571 'NextItState': pcStateReg('nextItstate', srtMode),
572 'Itstate': pcStateReg('itstate', srtMode),
573 'NextAArch64': pcStateReg('nextAArch64', srtMode),
574
575 #Register operands depending on a field in the instruction encoding. These
576 #should be avoided since they may not be portable across different
577 #encodings of the same instruction.
578 'Rd': intReg('RD'),
579 'Rm': intReg('RM'),
580 'Rs': intReg('RS'),
581 'Rn': intReg('RN'),
582 'Rt': intReg('RT')
583}};